From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sat, 1 May 2021 19:28:31 +0000 (+0100)
Subject: dcache store test: data goes in one cycle AFTER valid/addr set up
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=8dc517bf423e3d54a497bdb8af3943c5264f342b;p=soc.git

dcache store test: data goes in one cycle AFTER valid/addr set up
---

diff --git a/src/soc/experiment/dcache.py b/src/soc/experiment/dcache.py
index 67c5f8a6..c8104301 100644
--- a/src/soc/experiment/dcache.py
+++ b/src/soc/experiment/dcache.py
@@ -5,6 +5,9 @@ based on Anton Blanchard microwatt dcache.vhdl
 note that the microwatt dcache wishbone interface expects "stall".
 for simplicity at the moment this is hard-coded to cyc & ~ack.
 see WB4 spec, p84, section 5.2.1
+
+IMPORTANT: for store, the data is sampled the cycle AFTER the "valid"
+is raised.  sigh
 """
 
 import sys
@@ -1710,11 +1713,11 @@ def dcache_load(dut, addr, nc=0):
 def dcache_store(dut, addr, data, nc=0):
     yield dut.d_in.load.eq(0)
     yield dut.d_in.nc.eq(nc)
-    yield dut.d_in.data.eq(data)
     yield dut.d_in.byte_sel.eq(~0)
     yield dut.d_in.addr.eq(addr)
     yield dut.d_in.valid.eq(1)
     yield
+    yield dut.d_in.data.eq(data)    # leave set, but the cycle AFTER
     yield dut.d_in.valid.eq(0)
     yield dut.d_in.byte_sel.eq(0)
     while not (yield dut.d_out.valid):