From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Wed, 20 Mar 2019 14:16:41 +0000 (+0000)
Subject: use ispec/ospec in FPRoundMod
X-Git-Tag: ls180-24jan2020~1597
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=8dd56e33951f25ac08a05138f5fcda7923ab6336;p=ieee754fpu.git

use ispec/ospec in FPRoundMod
---

diff --git a/src/add/nmigen_add_experiment.py b/src/add/nmigen_add_experiment.py
index 9f897250..8331540a 100644
--- a/src/add/nmigen_add_experiment.py
+++ b/src/add/nmigen_add_experiment.py
@@ -1287,23 +1287,29 @@ class FPNormToPack(FPState, FPID):
 class FPRoundMod:
 
     def __init__(self, width):
-        self.in_roundz = Signal(reset_less=True)
-        self.in_z = FPNumBase(width, False)
-        self.out_z = FPNumBase(width, False)
+        self.width = width
+        self.i = self.ispec()
+        self.out_z = self.ospec()
+
+    def ispec(self):
+        return FPNorm1Data(self.width)
+
+    def ospec(self):
+        return FPNumBase(self.width, False)
 
     def setup(self, m, in_z, roundz):
         m.submodules.roundz = self
 
-        m.d.comb += self.in_z.eq(in_z)
-        m.d.comb += self.in_roundz.eq(roundz)
+        m.d.comb += self.i.z.eq(in_z)
+        m.d.comb += self.i.roundz.eq(roundz)
 
     def elaborate(self, platform):
         m = Module()
-        m.d.comb += self.out_z.eq(self.in_z)
-        with m.If(self.in_roundz):
-            m.d.comb += self.out_z.m.eq(self.in_z.m + 1) # mantissa rounds up
-            with m.If(self.in_z.m == self.in_z.m1s): # all 1s
-                m.d.comb += self.out_z.e.eq(self.in_z.e + 1) # exponent up
+        m.d.comb += self.out_z.eq(self.i.z)
+        with m.If(self.i.roundz):
+            m.d.comb += self.out_z.m.eq(self.i.z.m + 1) # mantissa rounds up
+            with m.If(self.i.z.m == self.i.z.m1s): # all 1s
+                m.d.comb += self.out_z.e.eq(self.i.z.e + 1) # exponent up
         return m