From: Tim Newsome <tim@sifive.com>
Date: Thu, 16 Feb 2017 04:41:06 +0000 (-0800)
Subject: Set cmderr when data is accessed while busy.
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=8dd673b74499d0195f6b1308a6709e05db6fa571;p=riscv-isa-sim.git

Set cmderr when data is accessed while busy.
---

diff --git a/riscv/debug_module.cc b/riscv/debug_module.cc
index 8d93e9e..af71974 100644
--- a/riscv/debug_module.cc
+++ b/riscv/debug_module.cc
@@ -221,6 +221,10 @@ bool debug_module_t::dmi_read(unsigned address, uint32_t *value)
     unsigned i = address - DMI_DATA0;
     result = dmdata.read32(4 * i);
 
+    if (abstractcs.busy && abstractcs.cmderr == abstractcs.CMDERR_NONE) {
+      abstractcs.cmderr = abstractcs.CMDERR_BUSY;
+    }
+
     bool autoexec = false;
     switch (i) {
       case 0:   autoexec = abstractcs.autoexec0; break;
@@ -376,6 +380,10 @@ bool debug_module_t::dmi_write(unsigned address, uint32_t value)
     unsigned i = address - DMI_DATA0;
     dmdata.write32(4 * i, value);
 
+    if (abstractcs.busy && abstractcs.cmderr == abstractcs.CMDERR_NONE) {
+      abstractcs.cmderr = abstractcs.CMDERR_BUSY;
+    }
+
     bool autoexec = false;
     switch (i) {
       case 0:   autoexec = abstractcs.autoexec0; break;