From: Eddie Hung <eddie@fpgeh.com>
Date: Mon, 25 May 2020 14:18:21 +0000 (-0700)
Subject: tests: add testcase for abc9 -dff preserving flop names
X-Git-Tag: working-ls180~507^2~6
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=8dd93e389eecebbe005886452cd60edefdbdc21a;p=yosys.git

tests: add testcase for abc9 -dff preserving flop names
---

diff --git a/tests/arch/xilinx/abc9_dff.ys b/tests/arch/xilinx/abc9_dff.ys
index fd343969b..c549e1fdc 100644
--- a/tests/arch/xilinx/abc9_dff.ys
+++ b/tests/arch/xilinx/abc9_dff.ys
@@ -82,4 +82,38 @@ select -assert-count 1 t:FDPE
 select -assert-count 2 t:INV
 select -assert-count 0 t:FD* t:INV %% t:* %D
 
+
+design -reset
+read_verilog <<EOT
+module top(input clk, input d, output q);
+reg r;
+always @(posedge clk) begin
+r <= d;
+end
+assign q = ~r;
+endmodule
+EOT
+proc
+equiv_opt -assert -multiclock -map +/xilinx/cells_sim.v synth_xilinx -abc9 -dff -noiopad -noclkbuf
+design -load postopt
+select -assert-count 1 t:FDRE %co w:r %i
+
+
+design -reset
+read_verilog <<EOT
+module top(input clk, input a, b, output reg q1, output q2);
+reg r;
+always @(posedge clk) begin
+    q1 <= a | b;
+    r <= ~(~a & ~b);
+end
+assign q2 = r;
+endmodule
+EOT
+proc
+equiv_opt -assert -multiclock -map +/xilinx/cells_sim.v synth_xilinx -abc9 -dff -noiopad -noclkbuf
+design -load postopt
+select -assert-count 1 t:FDRE %co %a w:r %i
+
+
 logger -expect-no-warnings