From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Wed, 28 Apr 2021 17:01:18 +0000 (+0000)
Subject: rename spblock modules to just straight spblock_512w64b8w after
X-Git-Tag: LS180_RC3~76
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=8dfc44f157d6b820759adf2149c8f826ddb20fe3;p=soclayout.git

rename spblock modules to just straight spblock_512w64b8w after
JP sorted blackbox module loading
---

diff --git a/experiments9/non_generated/full_core_4_4ksram_libresoc.v b/experiments9/non_generated/full_core_4_4ksram_libresoc.v
index 0d5f7fe..6f3af85 100644
--- a/experiments9/non_generated/full_core_4_4ksram_libresoc.v
+++ b/experiments9/non_generated/full_core_4_4ksram_libresoc.v
@@ -193401,7 +193401,7 @@ module sram4k_0(rst, enable, sram4k_0_wb__cyc, sram4k_0_wb__stb, sram4k_0_wb__ac
   assign \$1  = sram4k_0_wb__cyc & (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:56" *) sram4k_0_wb__stb;
   always @(posedge clk)
     sram4k_0_wb__ack <= \sram4k_0_wb__ack$next ;
-  spblock512w64b8w_0 spblock512w64b8w_0 (
+  spblock_512w64b8w spblock512w64b8w_0 (
     .a(a),
     .clk(clk),
     .d(d),
@@ -193545,7 +193545,7 @@ module sram4k_1(rst, enable, sram4k_1_wb__cyc, sram4k_1_wb__stb, sram4k_1_wb__ac
   assign \$1  = sram4k_1_wb__cyc & (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:56" *) sram4k_1_wb__stb;
   always @(posedge clk)
     sram4k_1_wb__ack <= \sram4k_1_wb__ack$next ;
-   spblock512w64b8w_1 spblock512w64b8w_1 (
+   spblock_512w64b8w spblock512w64b8w_1 (
     .a(a),
     .clk(clk),
     .d(d),
@@ -193689,7 +193689,7 @@ module sram4k_2(rst, enable, sram4k_2_wb__cyc, sram4k_2_wb__stb, sram4k_2_wb__ac
   assign \$1  = sram4k_2_wb__cyc & (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:56" *) sram4k_2_wb__stb;
   always @(posedge clk)
     sram4k_2_wb__ack <= \sram4k_2_wb__ack$next ;
-   spblock512w64b8w_2 spblock512w64b8w_2 (
+   spblock_512w64b8w spblock512w64b8w_2 (
     .a(a),
     .clk(clk),
     .d(d),
@@ -193833,7 +193833,7 @@ module sram4k_3(rst, enable, sram4k_3_wb__cyc, sram4k_3_wb__stb, sram4k_3_wb__ac
   assign \$1  = sram4k_3_wb__cyc & (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:56" *) sram4k_3_wb__stb;
   always @(posedge clk)
     sram4k_3_wb__ack <= \sram4k_3_wb__ack$next ;
-   spblock512w64b8w_3 spblock512w64b8w_3 (
+   spblock_512w64b8w spblock512w64b8w_3 (
     .a(a),
     .clk(clk),
     .d(d),
diff --git a/experiments9/non_generated/spblock512w64b8w.v b/experiments9/non_generated/spblock512w64b8w.v
index ef3870f..4555b15 100644
--- a/experiments9/non_generated/spblock512w64b8w.v
+++ b/experiments9/non_generated/spblock512w64b8w.v
@@ -1,5 +1,5 @@
 <* blackbox = 1 *)
-module spblock512w64b8w(a, d, q, we, clk);
+module spblock_512w64b8w(a, d, q, we, clk);
 	input [8:0] a;
 	input [63:0] d;
 	output [63:0] q;