From: Gabe Black <gabeblack@google.com>
Date: Wed, 18 Mar 2020 03:24:18 +0000 (-0700)
Subject: sparc: Make translateFunctional ignore alignment and use the page tables.
X-Git-Tag: v20.0.0.0~308
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=8e0e7da5ab399a3c2421d7c32349e2051774cec3;p=gem5.git

sparc: Make translateFunctional ignore alignment and use the page tables.

translateFunctional might be used with unaligned addresses which should
be allowed in that context. Also, in SE mode, if the translation isn't
in the TLB itself, then it should be looked up in the SE mode fake page
tables and not in a page table resident in memory.

Change-Id: Ibb39685cfdcd4eb6cb8a0486a1de014a4e452518
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/26831
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
---

diff --git a/src/arch/sparc/tlb.cc b/src/arch/sparc/tlb.cc
index 353a65c09..e67ae9aa7 100644
--- a/src/arch/sparc/tlb.cc
+++ b/src/arch/sparc/tlb.cc
@@ -42,8 +42,10 @@
 #include "debug/IPR.hh"
 #include "debug/TLB.hh"
 #include "mem/packet_access.hh"
+#include "mem/page_table.hh"
 #include "mem/request.hh"
 #include "sim/full_system.hh"
+#include "sim/process.hh"
 #include "sim/system.hh"
 
 /* @todo remove some of the magic constants.  -- ali
@@ -861,7 +863,6 @@ TLB::translateFunctional(const RequestPtr &req, ThreadContext *tc, Mode mode)
 
     bool real = (mode == Execute) ? inst_real : data_real;
 
-    PortProxy &mem = tc->getPhysProxy();
     TlbEntry* tbe;
     PageTableEntry pte;
     Addr tsbs[4];
@@ -873,9 +874,6 @@ TLB::translateFunctional(const RequestPtr &req, ThreadContext *tc, Mode mode)
         return NoFault;
     }
 
-    if (vaddr & (size - 1))
-        return std::make_shared<MemAddressNotAligned>();
-
     if (addr_mask)
         vaddr = vaddr & VAddrAMask;
 
@@ -895,6 +893,10 @@ TLB::translateFunctional(const RequestPtr &req, ThreadContext *tc, Mode mode)
         return NoFault;
     }
 
+    if (!FullSystem)
+        return tc->getProcessPtr()->pTable->translate(req);
+
+    PortProxy &mem = tc->getPhysProxy();
     // We didn't find it in the tlbs, so lets look at the TSBs
     GetTsbPtr(tc, vaddr, ctx_zero ? 0 : pri_context, tsbs);
     va_tag = bits(vaddr, 63, 22);