From: Jakub Jelinek Date: Tue, 1 Aug 2017 16:12:31 +0000 (+0200) Subject: re PR target/80846 (auto-vectorized AVX2 horizontal sum should narrow to 128b right... X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=8e1863eca8c8914cc5e05369dacdc5266cdca179;p=gcc.git re PR target/80846 (auto-vectorized AVX2 horizontal sum should narrow to 128b right away, to be more efficient for Ryzen and Intel) PR target/80846 * config/rs6000/vsx.md (vextract_fp_from_shorth, vextract_fp_from_shortl): Add element mode after mode in gen_vec_init* calls. From-SVN: r250784 --- diff --git a/gcc/ChangeLog b/gcc/ChangeLog index a6661bb12d9..5d33a594ed2 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,10 @@ +2017-08-01 Jakub Jelinek + + PR target/80846 + * config/rs6000/vsx.md (vextract_fp_from_shorth, + vextract_fp_from_shortl): Add element mode after mode in gen_vec_init* + calls. + 2017-08-01 Jerome Lambourg Doug Rupp Olivier Hainque diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md index 2937499c4a6..c2c1e925080 100644 --- a/gcc/config/rs6000/vsx.md +++ b/gcc/config/rs6000/vsx.md @@ -4523,7 +4523,7 @@ inputs in half words 1,3,5,7 (IBM numbering). Use xxperm to move src half words 0,1,2,3 for the conversion instruction. */ v = gen_rtvec_v (16, rvals); - emit_insn (gen_vec_initv16qi (mask, gen_rtx_PARALLEL (V16QImode, v))); + emit_insn (gen_vec_initv16qiqi (mask, gen_rtx_PARALLEL (V16QImode, v))); emit_insn (gen_altivec_vperm_v8hiv16qi (tmp, operands[1], operands[1], mask)); emit_insn (gen_vsx_xvcvhpsp (operands[0], tmp)); @@ -4552,7 +4552,7 @@ inputs in half words 1,3,5,7 (IBM numbering). Use xxperm to move src half words 4,5,6,7 for the conversion instruction. */ v = gen_rtvec_v (16, rvals); - emit_insn (gen_vec_initv16qi (mask, gen_rtx_PARALLEL (V16QImode, v))); + emit_insn (gen_vec_initv16qiqi (mask, gen_rtx_PARALLEL (V16QImode, v))); emit_insn (gen_altivec_vperm_v8hiv16qi (tmp, operands[1], operands[1], mask)); emit_insn (gen_vsx_xvcvhpsp (operands[0], tmp));