From: lkcl <lkcl@web>
Date: Sun, 23 Jun 2019 05:57:20 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: convert-csv-opcode-to-binary~4546
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=8e1b3155fdf80b3215960c1864b78ce1a41f13c3;p=libreriscv.git

---

diff --git a/simple_v_extension/specification.mdwn b/simple_v_extension/specification.mdwn
index 2d834fe47..5096baad8 100644
--- a/simple_v_extension/specification.mdwn
+++ b/simple_v_extension/specification.mdwn
@@ -79,7 +79,7 @@ The principle of SV is as follows:
   bit format (single instruction option) or a variable
  length VLIW-like prefix (multi or "grouped" option).
 * The prefix(es) indicate which registers are "tagged" as
-  "vectorised". Predicates can also be added.
+  "vectorised". Predicates can also be added, and element widths overridden on any src or dest register.
 * A "Vector Length" CSR is set, indicating the span of any future
   "parallel" operations.
 * If any operation (a **scalar** standard RV opcode) uses a register