From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Tue, 7 Apr 2020 15:54:50 +0000 (+0100)
Subject: op_fields is passed over (and excludes register names)
X-Git-Tag: div_pipeline~1435^2~47
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=8e261f6ee07e2ccf271f8838daa372d3e2dcb2ed;p=soc.git

op_fields is passed over (and excludes register names)
---

diff --git a/src/soc/decoder/isa/caller.py b/src/soc/decoder/isa/caller.py
index 90f1d764..647e58d6 100644
--- a/src/soc/decoder/isa/caller.py
+++ b/src/soc/decoder/isa/caller.py
@@ -177,11 +177,10 @@ class ISACaller:
         # then "yield" fields only from op_fields rather than hard-coded
         # list, here.
         fields = self.decoder.sigforms[formname]
-        for name in fields._fields:
-            if name not in ["RA", "RB", "RT"]:
-                sig = getattr(fields, name)
-                val = yield sig
-                self.namespace[name] = SelectableInt(val, sig.width)
+        for name in op_fields:
+            sig = getattr(fields, name)
+            val = yield sig
+            self.namespace[name] = SelectableInt(val, sig.width)
 
     def call(self, name):
         # TODO, asmregs is from the spec, e.g. add RT,RA,RB