From: whitequark Date: Sun, 23 Dec 2018 07:17:33 +0000 (+0000) Subject: back.rtlil: only translate switch tests once. X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=8e2690af264ea29d97dd81a8bbb7db37aa8d6d97;p=nmigen.git back.rtlil: only translate switch tests once. This seems to affect synthesis with Yosys but only marginally. It is mostly a speed and readability improvement. --- diff --git a/nmigen/back/rtlil.py b/nmigen/back/rtlil.py index 2c2f1ad..817f9b2 100644 --- a/nmigen/back/rtlil.py +++ b/nmigen/back/rtlil.py @@ -529,6 +529,8 @@ class _StatementCompiler(xfrm.StatementVisitor): self._group = None self._case = None + self._test_cache = {} + @contextmanager def case(self, switch, value): try: @@ -556,7 +558,11 @@ class _StatementCompiler(xfrm.StatementVisitor): self._case.assign(self.lhs_compiler(stmt.lhs), rhs_sigspec) def on_Switch(self, stmt): - with self._case.switch(self.rhs_compiler(stmt.test)) as switch: + if stmt not in self._test_cache: + self._test_cache[stmt] = self.rhs_compiler(stmt.test) + test_sigspec = self._test_cache[stmt] + + with self._case.switch(test_sigspec) as switch: for value, stmts in stmt.cases.items(): with self.case(switch, value): self.on_statements(stmts)