From: Nathanael Premillieu <npremill@irisa.fr>
Date: Wed, 21 Mar 2012 15:34:06 +0000 (-0500)
Subject: ARM: Fix case where cond/uncond control is mis-specified
X-Git-Tag: stable_2012_06_28~163
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=8e2a8fbb7e4751260c88fccd19ebe8d1138d0695;p=gem5.git

ARM: Fix case where cond/uncond control is mis-specified
---

diff --git a/src/arch/arm/isa/templates/pred.isa b/src/arch/arm/isa/templates/pred.isa
index 8d9d16492..efb8e470b 100644
--- a/src/arch/arm/isa/templates/pred.isa
+++ b/src/arch/arm/isa/templates/pred.isa
@@ -112,9 +112,9 @@ def template DataRegConstructor {{
             flags[IsControl] = true;
             flags[IsIndirectControl] = true;
             if (condCode == COND_AL || condCode == COND_UC)
-                flags[IsCondControl] = true;
-            else
                 flags[IsUncondControl] = true;
+            else
+                flags[IsCondControl] = true;
         }
 
         if (%(is_ras_pop)s) {