From: Cesar Strauss Date: Sun, 21 Feb 2021 17:21:54 +0000 (-0300) Subject: The field selection function was moved to nmutil.util X-Git-Tag: convert-csv-opcode-to-binary~174 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=8e30713ebb4d4cd17350401d85692b8fed1dbbab;p=soc.git The field selection function was moved to nmutil.util All previous users were updated. --- diff --git a/src/soc/consts.py b/src/soc/consts.py index c89fed93..ce13b3e1 100644 --- a/src/soc/consts.py +++ b/src/soc/consts.py @@ -80,32 +80,6 @@ def field(r, msb0_start, msb0_end=None, field_width=64): return r[field_slice(msb0_start, msb0_end, field_width)] -def sel(r, sel_bits, field_width=None): - """Forms a subfield from a selection of bits of the signal `r` - ("register"). - - :param r: signal containing the field from which to select the subfield - :param sel_bits: bit indices of the subfield, in "MSB 0" convention, - from most significant to least significant. Note that - the indices are allowed to be non-contiguous and - out-of-order. - :param field_width: field width. If absent, use the signal `r` own width. - """ - # find the MSB index in LSB0 numbering - if field_width is None: - msb = len(r) - 1 - else: - msb = field_width - 1 - # extract the selected bits - sig_list = [] - for idx in sel_bits: - sig_list.append(r[msb - idx]) - # place the LSB at the front of the list, - # since, in nMigen, Cat starts from the LSB - sig_list.reverse() - return Cat(*sig_list) - - # Listed in V3.0B Book III Chap 4.2.1 # MSR bit numbers, *bigendian* order (PowerISA format) # use this in the simulator