From: Cesar Strauss <cestrauss@gmail.com>
Date: Mon, 6 Jul 2020 10:49:05 +0000 (-0300)
Subject: Simplify waiting loops
X-Git-Tag: div_pipeline~162^2~40
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=8e3dccbdb3c71b151db2398c90b75906f2c225db;p=soc.git

Simplify waiting loops
---

diff --git a/src/soc/experiment/alu_hier.py b/src/soc/experiment/alu_hier.py
index c01b7f8a..d18f195a 100644
--- a/src/soc/experiment/alu_hier.py
+++ b/src/soc/experiment/alu_hier.py
@@ -413,20 +413,13 @@ def run_op(dut, a, b, op, inv_a=0):
     yield
 
     # wait for the ALU to accept our input data
-    while True:
-        rdy = yield dut.p.ready_o
-        if rdy:
-            break
+    while not (yield dut.p.ready_o):
         yield
 
     yield dut.p.valid_i.eq(0)
 
     # wait for the ALU to present the output data
-    while True:
-        yield Settle()
-        vld = yield dut.n.valid_o
-        if vld:
-            break
+    while not (yield dut.n.valid_o):
         yield
 
     # latch the result and lower read_i