From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sat, 27 Jun 2020 19:12:55 +0000 (+0100)
Subject: increase (double) address width in TstL0CacheBuffer
X-Git-Tag: div_pipeline~235
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=8e3fd4d0be5cba1ebc530858786a81136e8c6271;p=soc.git

increase (double) address width in TstL0CacheBuffer
---

diff --git a/src/soc/fu/compunits/test/test_compunit.py b/src/soc/fu/compunits/test/test_compunit.py
index 37258ea3..7b4c41cf 100644
--- a/src/soc/fu/compunits/test/test_compunit.py
+++ b/src/soc/fu/compunits/test/test_compunit.py
@@ -160,7 +160,8 @@ class TestRunner(FHDLTestCase):
         if self.funit == Function.LDST:
             from soc.experiment.l0_cache import TstL0CacheBuffer
             m.submodules.l0 = l0 = TstL0CacheBuffer(n_units=1, regwid=64,
-                                                    addrwid=3)
+                                                    addrwid=3,
+                                                    ifacetype='test_bare_wb')
             pi = l0.l0.dports[0]
             m.submodules.cu = cu = self.fukls(pi, awid=3)
             m.d.comb += cu.ad.go.eq(cu.ad.rel) # link addr-go direct to rel