From: Doug Evans <dje@google.com>
Date: Tue, 20 Jan 1998 10:43:16 +0000 (+0000)
Subject: 	* Makefile.in: Add m32rx objs, and rules to build them.
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=8e420152668df27fe1a30447e438dc13e85560ac;p=binutils-gdb.git

	* Makefile.in: Add m32rx objs, and rules to build them.
	* cpux.h, decodex.h, decodex.c, readx.c, semx.c, modelx.c: New files.
	* m32rx.c, mloopx.in: New files.
---

diff --git a/sim/m32r/ChangeLog b/sim/m32r/ChangeLog
index a9ed0b21461..ad72a2bdfdc 100644
--- a/sim/m32r/ChangeLog
+++ b/sim/m32r/ChangeLog
@@ -1,3 +1,11 @@
+Tue Jan 20 01:42:17 1998  Doug Evans  <devans@seba.cygnus.com>
+
+start-sanitize-m32rx
+	* Makefile.in: Add m32rx objs, and rules to build them.
+	* cpux.h, decodex.h, decodex.c, readx.c, semx.c, modelx.c: New files.
+	* m32rx.c, mloopx.in: New files.
+end-sanitize-m32rx
+
 Mon Jan 19 22:26:29 1998  Doug Evans  <devans@seba>
 
 	* configure: Regenerated to track ../common/aclocal.m4 changes.
diff --git a/sim/m32r/Makefile.in b/sim/m32r/Makefile.in
index a848a252968..458e44348e6 100644
--- a/sim/m32r/Makefile.in
+++ b/sim/m32r/Makefile.in
@@ -22,7 +22,7 @@
 
 M32R_OBJS = m32r.o decode.o extract.o sem.o model.o mloop.o
 # start-sanitize-m32rx
-M32RX_OBJS = m32rx.o decodex.o modelx.o mloopx.o
+M32RX_OBJS = m32rx.o decodex.o semx.o modelx.o mloopx.o
 # end-sanitize-m32rx
 
 SIM_OBJS = \
@@ -30,6 +30,9 @@ SIM_OBJS = \
 	sim-hload.o sim-hrw.o sim-engine.o sim-model.o sim-reason.o \
 	cgen-utils.o cgen-trace.o cgen-scache.o \
 	sim-if.o arch.o \
+	$(start-sanitize-m32rx) \
+	$(M32RX_OBJS) \
+	$(end-sanitize-m32rx) \
 	$(M32R_OBJS)
 
 # Extra headers included by sim-main.h.
@@ -93,7 +96,7 @@ sem-cache.o: sem.c decode.h $(INCLUDE_DEPS) $(OPS_INCLUDE_DEPS) cpu.h
 mloopx.c: $(srcdir)/../common/genmloop.sh mloopx.in Makefile
 	rm -f mloopx.c
 	$(SHELL) $(srcdir)/../common/genmloop.sh $(SHELL) -mono -no-scache -no-fast -parallel m32r $(srcdir)/mloopx.in | sed -e 's/@cpu@/m32rx/' -e 's/@CPU@/M32RX/' >mloopx.c
-mloopx.o: mloopx.c readx.c semx-switch.c $(INCLUDE_DEPS) $(OPS_INCLUDE_DEPS) cpux.h
+mloopx.o: mloopx.c readx.c $(INCLUDE_DEPS) $(OPS_INCLUDE_DEPS) cpux.h
 
 decodex.o: decodex.c decodex.h $(INCLUDE_DEPS) $(OPS_INCLUDE_DEPS) cpu-opc.h cpux.h
 extractx.o: extractx.c decodex.h $(INCLUDE_DEPS) $(OPS_INCLUDE_DEPS) cpux.h
@@ -140,9 +143,9 @@ decode.h decode.c: @MAINT@ stamp-decode
 
 # start-sanitize-m32rx
 stamp-xcpu: $(CGEN_MAIN_SCM) $(CGEN_CPU_SCM) $(srccgen)/m32r.cpu
-	$(MAKE) cgen-cpu cpu=m32rx mach=m32rx SUFFIX=x FLAGS="" EXTRAFILES="$(CGEN_CPU_READ) $(CGEN_CPU_SEMSW)"
+	$(MAKE) cgen-cpu cpu=m32rx mach=m32rx SUFFIX=x FLAGS="" EXTRAFILES="$(CGEN_CPU_READ) $(CGEN_CPU_SEM)"
 	touch stamp-xcpu
-cpux.h readx.c semx-switch.c modelx.c: @MAINT@ stamp-xcpu
+cpux.h readx.c semx.c modelx.c: @MAINT@ stamp-xcpu
 	@true
 
 stamp-xdecode: $(CGEN_MAIN_SCM) $(CGEN_DECODE_SCM) $(srccgen)/m32r.cpu
diff --git a/sim/m32r/cpux.h b/sim/m32r/cpux.h
new file mode 100644
index 00000000000..37332b5d4ef
--- /dev/null
+++ b/sim/m32r/cpux.h
@@ -0,0 +1,1389 @@
+/* CPU family header for m32rx.
+
+Copyright (C) 1996, 1997, 1998 Free Software Foundation, Inc.
+
+This file is part of the GNU Simulators.
+
+This program is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2, or (at your option)
+any later version.
+
+This program is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License along
+with this program; if not, write to the Free Software Foundation, Inc.,
+59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+
+*/
+
+#ifndef CPU_M32RX_H
+#define CPU_M32RX_H
+
+/* Maximum number of instructions that are fetched at a time.
+   This is for LIW type instructions sets (e.g. m32r).  */
+#define MAX_LIW_INSNS 2
+
+/* Maximum number of instructions that can be executed in parallel.  */
+#define MAX_PARALLEL_INSNS 2
+
+/* CPU state information.  */
+typedef struct {
+  /* Hardware elements.  */
+  struct {
+  /* program counter */
+  USI h_pc;
+#define GET_H_PC() CPU (h_pc)
+#define SET_H_PC(x) (CPU (h_pc) = (x))
+  /* general registers */
+  SI h_gr[16];
+#define GET_H_GR(a1) CPU (h_gr)[a1]
+#define SET_H_GR(a1, x) (CPU (h_gr)[a1] = (x))
+  /* control registers */
+  SI h_cr[7];
+#define GET_H_CR(a1) CPU (h_cr)[a1]
+#define SET_H_CR(a1, x) (CPU (h_cr)[a1] = (x))
+  /* accumulator */
+  DI h_accum;
+#define GET_H_ACCUM() CPU (h_accum)
+#define SET_H_ACCUM(x) (CPU (h_accum) = (x))
+  /* accumulators */
+  DI h_accums[2];
+#define GET_H_ACCUMS(a1) CPU (h_accums)[a1]
+#define SET_H_ACCUMS(a1, x) (CPU (h_accums)[a1] = (x))
+  /* abort flag */
+  UBI h_abort;
+#define GET_H_ABORT() CPU (h_abort)
+#define SET_H_ABORT(x) (CPU (h_abort) = (x))
+  /* condition bit */
+  UBI h_cond;
+#define GET_H_COND() CPU (h_cond)
+#define SET_H_COND(x) (CPU (h_cond) = (x))
+  /* sm */
+  UBI h_sm;
+#define GET_H_SM() CPU (h_sm)
+#define SET_H_SM(x) (CPU (h_sm) = (x))
+  /* bsm */
+  UBI h_bsm;
+#define GET_H_BSM() CPU (h_bsm)
+#define SET_H_BSM(x) (CPU (h_bsm) = (x))
+  /* ie */
+  UBI h_ie;
+#define GET_H_IE() CPU (h_ie)
+#define SET_H_IE(x) (CPU (h_ie) = (x))
+  /* bie */
+  UBI h_bie;
+#define GET_H_BIE() CPU (h_bie)
+#define SET_H_BIE(x) (CPU (h_bie) = (x))
+  /* bcond */
+  UBI h_bcond;
+#define GET_H_BCOND() CPU (h_bcond)
+#define SET_H_BCOND(x) (CPU (h_bcond) = (x))
+  /* bpc */
+  SI h_bpc;
+#define GET_H_BPC() CPU (h_bpc)
+#define SET_H_BPC(x) (CPU (h_bpc) = (x))
+  } hardware;
+#define CPU_CGEN_HW(cpu) (& (cpu)->cpu_data.hardware)
+  /* CPU profiling state information.  */
+  struct {
+  /* general registers */
+  unsigned long h_gr;
+  } profile;
+#define CPU_CGEN_PROFILE(cpu) (& (cpu)->cpu_data.profile)
+} M32RX_CPU_DATA;
+
+/* FIXME: length parm to decode() is currently unneeded.  */
+extern DECODE *m32rx_decode (SIM_CPU *, insn_t /*, int*/);
+
+/* The ARGBUF struct.  */
+struct argbuf {
+  /* These are the baseclass definitions.  */
+  unsigned int length;
+  PCADDR addr;
+  const struct cgen_insn *opcode;
+  /* unsigned long insn; - no longer needed */
+  /* cpu specific data follows */
+  union {
+    struct { /* e.g. add $dr,$sr */
+      UINT f_r1;
+      UINT f_r2;
+    } fmt_0_add;
+    struct { /* e.g. add3 $dr,$sr,#$slo16 */
+      UINT f_r1;
+      UINT f_r2;
+      HI f_simm16;
+    } fmt_1_add3;
+    struct { /* e.g. and3 $dr,$sr,#$uimm16 */
+      UINT f_r1;
+      UINT f_r2;
+      USI f_uimm16;
+    } fmt_2_and3;
+    struct { /* e.g. or3 $dr,$sr,#$ulo16 */
+      UINT f_r1;
+      UINT f_r2;
+      UHI f_uimm16;
+    } fmt_3_or3;
+    struct { /* e.g. addi $dr,#$simm8 */
+      UINT f_r1;
+      SI f_simm8;
+    } fmt_4_addi;
+    struct { /* e.g. addv3 $dr,$sr,#$simm16 */
+      UINT f_r1;
+      UINT f_r2;
+      SI f_simm16;
+    } fmt_5_addv3;
+    struct { /* e.g. addx $dr,$sr */
+      UINT f_r1;
+      UINT f_r2;
+    } fmt_6_addx;
+    struct { /* e.g. bc $disp8 */
+      IADDR f_disp8;
+    } fmt_7_bc8;
+    struct { /* e.g. bc $disp24 */
+      IADDR f_disp24;
+    } fmt_8_bc24;
+    struct { /* e.g. beq $src1,$src2,$disp16 */
+      UINT f_r1;
+      UINT f_r2;
+      IADDR f_disp16;
+    } fmt_9_beq;
+    struct { /* e.g. beqz $src2,$disp16 */
+      UINT f_r2;
+      IADDR f_disp16;
+    } fmt_10_beqz;
+    struct { /* e.g. bl $disp8 */
+      IADDR f_disp8;
+    } fmt_11_bl8;
+    struct { /* e.g. bl $disp24 */
+      IADDR f_disp24;
+    } fmt_12_bl24;
+    struct { /* e.g. bcl $disp8 */
+      IADDR f_disp8;
+    } fmt_13_bcl8;
+    struct { /* e.g. bcl $disp24 */
+      IADDR f_disp24;
+    } fmt_14_bcl24;
+    struct { /* e.g. bra $disp8 */
+      IADDR f_disp8;
+    } fmt_15_bra8;
+    struct { /* e.g. bra $disp24 */
+      IADDR f_disp24;
+    } fmt_16_bra24;
+    struct { /* e.g. cmp $src1,$src2 */
+      UINT f_r1;
+      UINT f_r2;
+    } fmt_17_cmp;
+    struct { /* e.g. cmpi $src2,#$simm16 */
+      UINT f_r2;
+      SI f_simm16;
+    } fmt_18_cmpi;
+    struct { /* e.g. cmpui $src2,#$uimm16 */
+      UINT f_r2;
+      USI f_uimm16;
+    } fmt_19_cmpui;
+    struct { /* e.g. cmpz $src2 */
+      UINT f_r2;
+    } fmt_20_cmpz;
+    struct { /* e.g. div $dr,$sr */
+      UINT f_r1;
+      UINT f_r2;
+    } fmt_21_div;
+    struct { /* e.g. jc $sr */
+      UINT f_r2;
+    } fmt_22_jc;
+    struct { /* e.g. jl $sr */
+      UINT f_r2;
+    } fmt_23_jl;
+    struct { /* e.g. jmp $sr */
+      UINT f_r2;
+    } fmt_24_jmp;
+    struct { /* e.g. ld $dr,@$sr */
+      UINT f_r1;
+      UINT f_r2;
+    } fmt_25_ld;
+    struct { /* e.g. ld $dr,@($slo16,$sr) */
+      UINT f_r1;
+      UINT f_r2;
+      HI f_simm16;
+    } fmt_26_ld_d;
+    struct { /* e.g. ldb $dr,@$sr */
+      UINT f_r1;
+      UINT f_r2;
+    } fmt_27_ldb;
+    struct { /* e.g. ldb $dr,@($slo16,$sr) */
+      UINT f_r1;
+      UINT f_r2;
+      HI f_simm16;
+    } fmt_28_ldb_d;
+    struct { /* e.g. ldh $dr,@$sr */
+      UINT f_r1;
+      UINT f_r2;
+    } fmt_29_ldh;
+    struct { /* e.g. ldh $dr,@($slo16,$sr) */
+      UINT f_r1;
+      UINT f_r2;
+      HI f_simm16;
+    } fmt_30_ldh_d;
+    struct { /* e.g. ld24 $dr,#$uimm24 */
+      UINT f_r1;
+      ADDR f_uimm24;
+    } fmt_31_ld24;
+    struct { /* e.g. ldi $dr,#$simm8 */
+      UINT f_r1;
+      SI f_simm8;
+    } fmt_32_ldi8;
+    struct { /* e.g. ldi $dr,$slo16 */
+      UINT f_r1;
+      HI f_simm16;
+    } fmt_33_ldi16;
+    struct { /* e.g. machi $src1,$src2 */
+      UINT f_r1;
+      UINT f_r2;
+    } fmt_34_machi;
+    struct { /* e.g. machi $src1,$src2,$acc */
+      UINT f_r1;
+      UINT f_acc;
+      UINT f_r2;
+    } fmt_35_machi_a;
+    struct { /* e.g. mulhi $src1,$src2,$acc */
+      UINT f_r1;
+      UINT f_acc;
+      UINT f_r2;
+    } fmt_36_mulhi_a;
+    struct { /* e.g. mv $dr,$sr */
+      UINT f_r1;
+      UINT f_r2;
+    } fmt_37_mv;
+    struct { /* e.g. mvfachi $dr */
+      UINT f_r1;
+    } fmt_38_mvfachi;
+    struct { /* e.g. mvfachi $dr,$accs */
+      UINT f_r1;
+      UINT f_accs;
+    } fmt_39_mvfachi_a;
+    struct { /* e.g. mvfc $dr,$scr */
+      UINT f_r1;
+      UINT f_r2;
+    } fmt_40_mvfc;
+    struct { /* e.g. mvtachi $src1 */
+      UINT f_r1;
+    } fmt_41_mvtachi;
+    struct { /* e.g. mvtachi $src1,$accs */
+      UINT f_r1;
+      UINT f_accs;
+    } fmt_42_mvtachi_a;
+    struct { /* e.g. mvtc $sr,$dcr */
+      UINT f_r1;
+      UINT f_r2;
+    } fmt_43_mvtc;
+    struct { /* e.g. nop */
+      int empty;
+    } fmt_44_nop;
+    struct { /* e.g. rac */
+      int empty;
+    } fmt_45_rac;
+    struct { /* e.g. rac $accs */
+      UINT f_accs;
+    } fmt_46_rac_a;
+    struct { /* e.g. seth $dr,$hi16 */
+      UINT f_r1;
+      UHI f_hi16;
+    } fmt_47_seth;
+    struct { /* e.g. slli $dr,#$uimm5 */
+      UINT f_r1;
+      USI f_uimm5;
+    } fmt_48_slli;
+    struct { /* e.g. st $src1,@($slo16,$src2) */
+      UINT f_r1;
+      UINT f_r2;
+      HI f_simm16;
+    } fmt_49_st_d;
+    struct { /* e.g. trap #$uimm4 */
+      USI f_uimm4;
+    } fmt_50_trap;
+    struct { /* e.g. satb $dr,$src2 */
+      UINT f_r1;
+      UINT f_r2;
+    } fmt_51_satb;
+    struct { /* e.g. pcmpbz $src2 */
+      UINT f_r2;
+    } fmt_52_pcmpbz;
+    struct { /* e.g. sadd */
+      int empty;
+    } fmt_53_sadd;
+    struct { /* e.g. macwu1 $src1,$src2 */
+      UINT f_r1;
+      UINT f_r2;
+    } fmt_54_macwu1;
+    struct { /* e.g. sc */
+      int empty;
+    } fmt_55_sc;
+  } fields;
+#if 1 || WITH_PROFILE_MODEL_P /*FIXME:wip*/
+  unsigned long h_gr_get;
+  unsigned long h_gr_set;
+#endif
+};
+
+/* A cached insn.
+   This is also used in the non-scache case.  In this situation we assume
+   the cache size is 1, and do a few things a little differently.  */
+
+struct scache {
+  IADDR next;
+  union {
+#if ! WITH_SEM_SWITCH_FULL
+    SEMANTIC_FN *sem_fn;
+#endif
+#if ! WITH_SEM_SWITCH_FAST
+#if WITH_SCACHE
+    SEMANTIC_CACHE_FN *sem_fast_fn;
+#else
+    SEMANTIC_FN *sem_fast_fn;
+#endif
+#endif
+#if WITH_SEM_SWITCH_FULL || WITH_SEM_SWITCH_FAST
+#ifdef __GNUC__
+    void *sem_case;
+#else
+    int sem_case;
+#endif
+#endif
+  } semantic;
+  struct argbuf argbuf;
+};
+
+/* Macros to simplify extraction, reading and semantic code.
+   These define and assign the local vars that contain the insn's fields.  */
+
+#define EXTRACT_FMT_0_ADD_VARS \
+  /* Instruction fields.  */ \
+  UINT f_op1; \
+  UINT f_r1; \
+  UINT f_op2; \
+  UINT f_r2; \
+  unsigned int length;
+#define EXTRACT_FMT_0_ADD_CODE \
+  length = 2; \
+  f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
+  f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
+  f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
+  f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
+
+#define EXTRACT_FMT_1_ADD3_VARS \
+  /* Instruction fields.  */ \
+  UINT f_op1; \
+  UINT f_r1; \
+  UINT f_op2; \
+  UINT f_r2; \
+  int f_simm16; \
+  unsigned int length;
+#define EXTRACT_FMT_1_ADD3_CODE \
+  length = 4; \
+  f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
+  f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
+  f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4); \
+  f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
+  f_simm16 = EXTRACT_SIGNED (insn, 32, 16, 16); \
+
+#define EXTRACT_FMT_2_AND3_VARS \
+  /* Instruction fields.  */ \
+  UINT f_op1; \
+  UINT f_r1; \
+  UINT f_op2; \
+  UINT f_r2; \
+  UINT f_uimm16; \
+  unsigned int length;
+#define EXTRACT_FMT_2_AND3_CODE \
+  length = 4; \
+  f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
+  f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
+  f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4); \
+  f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
+  f_uimm16 = EXTRACT_UNSIGNED (insn, 32, 16, 16); \
+
+#define EXTRACT_FMT_3_OR3_VARS \
+  /* Instruction fields.  */ \
+  UINT f_op1; \
+  UINT f_r1; \
+  UINT f_op2; \
+  UINT f_r2; \
+  UINT f_uimm16; \
+  unsigned int length;
+#define EXTRACT_FMT_3_OR3_CODE \
+  length = 4; \
+  f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
+  f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
+  f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4); \
+  f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
+  f_uimm16 = EXTRACT_UNSIGNED (insn, 32, 16, 16); \
+
+#define EXTRACT_FMT_4_ADDI_VARS \
+  /* Instruction fields.  */ \
+  UINT f_op1; \
+  UINT f_r1; \
+  int f_simm8; \
+  unsigned int length;
+#define EXTRACT_FMT_4_ADDI_CODE \
+  length = 2; \
+  f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
+  f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
+  f_simm8 = EXTRACT_SIGNED (insn, 16, 8, 8); \
+
+#define EXTRACT_FMT_5_ADDV3_VARS \
+  /* Instruction fields.  */ \
+  UINT f_op1; \
+  UINT f_r1; \
+  UINT f_op2; \
+  UINT f_r2; \
+  int f_simm16; \
+  unsigned int length;
+#define EXTRACT_FMT_5_ADDV3_CODE \
+  length = 4; \
+  f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
+  f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
+  f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4); \
+  f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
+  f_simm16 = EXTRACT_SIGNED (insn, 32, 16, 16); \
+
+#define EXTRACT_FMT_6_ADDX_VARS \
+  /* Instruction fields.  */ \
+  UINT f_op1; \
+  UINT f_r1; \
+  UINT f_op2; \
+  UINT f_r2; \
+  unsigned int length;
+#define EXTRACT_FMT_6_ADDX_CODE \
+  length = 2; \
+  f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
+  f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
+  f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
+  f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
+
+#define EXTRACT_FMT_7_BC8_VARS \
+  /* Instruction fields.  */ \
+  UINT f_op1; \
+  UINT f_r1; \
+  int f_disp8; \
+  unsigned int length;
+#define EXTRACT_FMT_7_BC8_CODE \
+  length = 2; \
+  f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
+  f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
+  f_disp8 = EXTRACT_SIGNED (insn, 16, 8, 8) << 2; \
+
+#define EXTRACT_FMT_8_BC24_VARS \
+  /* Instruction fields.  */ \
+  UINT f_op1; \
+  UINT f_r1; \
+  int f_disp24; \
+  unsigned int length;
+#define EXTRACT_FMT_8_BC24_CODE \
+  length = 4; \
+  f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
+  f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
+  f_disp24 = EXTRACT_SIGNED (insn, 32, 8, 24) << 2; \
+
+#define EXTRACT_FMT_9_BEQ_VARS \
+  /* Instruction fields.  */ \
+  UINT f_op1; \
+  UINT f_r1; \
+  UINT f_op2; \
+  UINT f_r2; \
+  int f_disp16; \
+  unsigned int length;
+#define EXTRACT_FMT_9_BEQ_CODE \
+  length = 4; \
+  f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
+  f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
+  f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4); \
+  f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
+  f_disp16 = EXTRACT_SIGNED (insn, 32, 16, 16) << 2; \
+
+#define EXTRACT_FMT_10_BEQZ_VARS \
+  /* Instruction fields.  */ \
+  UINT f_op1; \
+  UINT f_r1; \
+  UINT f_op2; \
+  UINT f_r2; \
+  int f_disp16; \
+  unsigned int length;
+#define EXTRACT_FMT_10_BEQZ_CODE \
+  length = 4; \
+  f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
+  f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
+  f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4); \
+  f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
+  f_disp16 = EXTRACT_SIGNED (insn, 32, 16, 16) << 2; \
+
+#define EXTRACT_FMT_11_BL8_VARS \
+  /* Instruction fields.  */ \
+  UINT f_op1; \
+  UINT f_r1; \
+  int f_disp8; \
+  unsigned int length;
+#define EXTRACT_FMT_11_BL8_CODE \
+  length = 2; \
+  f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
+  f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
+  f_disp8 = EXTRACT_SIGNED (insn, 16, 8, 8) << 2; \
+
+#define EXTRACT_FMT_12_BL24_VARS \
+  /* Instruction fields.  */ \
+  UINT f_op1; \
+  UINT f_r1; \
+  int f_disp24; \
+  unsigned int length;
+#define EXTRACT_FMT_12_BL24_CODE \
+  length = 4; \
+  f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
+  f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
+  f_disp24 = EXTRACT_SIGNED (insn, 32, 8, 24) << 2; \
+
+#define EXTRACT_FMT_13_BCL8_VARS \
+  /* Instruction fields.  */ \
+  UINT f_op1; \
+  UINT f_r1; \
+  int f_disp8; \
+  unsigned int length;
+#define EXTRACT_FMT_13_BCL8_CODE \
+  length = 2; \
+  f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
+  f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
+  f_disp8 = EXTRACT_SIGNED (insn, 16, 8, 8) << 2; \
+
+#define EXTRACT_FMT_14_BCL24_VARS \
+  /* Instruction fields.  */ \
+  UINT f_op1; \
+  UINT f_r1; \
+  int f_disp24; \
+  unsigned int length;
+#define EXTRACT_FMT_14_BCL24_CODE \
+  length = 4; \
+  f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
+  f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
+  f_disp24 = EXTRACT_SIGNED (insn, 32, 8, 24) << 2; \
+
+#define EXTRACT_FMT_15_BRA8_VARS \
+  /* Instruction fields.  */ \
+  UINT f_op1; \
+  UINT f_r1; \
+  int f_disp8; \
+  unsigned int length;
+#define EXTRACT_FMT_15_BRA8_CODE \
+  length = 2; \
+  f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
+  f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
+  f_disp8 = EXTRACT_SIGNED (insn, 16, 8, 8) << 2; \
+
+#define EXTRACT_FMT_16_BRA24_VARS \
+  /* Instruction fields.  */ \
+  UINT f_op1; \
+  UINT f_r1; \
+  int f_disp24; \
+  unsigned int length;
+#define EXTRACT_FMT_16_BRA24_CODE \
+  length = 4; \
+  f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
+  f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
+  f_disp24 = EXTRACT_SIGNED (insn, 32, 8, 24) << 2; \
+
+#define EXTRACT_FMT_17_CMP_VARS \
+  /* Instruction fields.  */ \
+  UINT f_op1; \
+  UINT f_r1; \
+  UINT f_op2; \
+  UINT f_r2; \
+  unsigned int length;
+#define EXTRACT_FMT_17_CMP_CODE \
+  length = 2; \
+  f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
+  f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
+  f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
+  f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
+
+#define EXTRACT_FMT_18_CMPI_VARS \
+  /* Instruction fields.  */ \
+  UINT f_op1; \
+  UINT f_r1; \
+  UINT f_op2; \
+  UINT f_r2; \
+  int f_simm16; \
+  unsigned int length;
+#define EXTRACT_FMT_18_CMPI_CODE \
+  length = 4; \
+  f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
+  f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
+  f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4); \
+  f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
+  f_simm16 = EXTRACT_SIGNED (insn, 32, 16, 16); \
+
+#define EXTRACT_FMT_19_CMPUI_VARS \
+  /* Instruction fields.  */ \
+  UINT f_op1; \
+  UINT f_r1; \
+  UINT f_op2; \
+  UINT f_r2; \
+  UINT f_uimm16; \
+  unsigned int length;
+#define EXTRACT_FMT_19_CMPUI_CODE \
+  length = 4; \
+  f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
+  f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
+  f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4); \
+  f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
+  f_uimm16 = EXTRACT_UNSIGNED (insn, 32, 16, 16); \
+
+#define EXTRACT_FMT_20_CMPZ_VARS \
+  /* Instruction fields.  */ \
+  UINT f_op1; \
+  UINT f_r1; \
+  UINT f_op2; \
+  UINT f_r2; \
+  unsigned int length;
+#define EXTRACT_FMT_20_CMPZ_CODE \
+  length = 2; \
+  f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
+  f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
+  f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
+  f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
+
+#define EXTRACT_FMT_21_DIV_VARS \
+  /* Instruction fields.  */ \
+  UINT f_op1; \
+  UINT f_r1; \
+  UINT f_op2; \
+  UINT f_r2; \
+  int f_simm16; \
+  unsigned int length;
+#define EXTRACT_FMT_21_DIV_CODE \
+  length = 4; \
+  f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
+  f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
+  f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4); \
+  f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
+  f_simm16 = EXTRACT_SIGNED (insn, 32, 16, 16); \
+
+#define EXTRACT_FMT_22_JC_VARS \
+  /* Instruction fields.  */ \
+  UINT f_op1; \
+  UINT f_r1; \
+  UINT f_op2; \
+  UINT f_r2; \
+  unsigned int length;
+#define EXTRACT_FMT_22_JC_CODE \
+  length = 2; \
+  f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
+  f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
+  f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
+  f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
+
+#define EXTRACT_FMT_23_JL_VARS \
+  /* Instruction fields.  */ \
+  UINT f_op1; \
+  UINT f_r1; \
+  UINT f_op2; \
+  UINT f_r2; \
+  unsigned int length;
+#define EXTRACT_FMT_23_JL_CODE \
+  length = 2; \
+  f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
+  f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
+  f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
+  f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
+
+#define EXTRACT_FMT_24_JMP_VARS \
+  /* Instruction fields.  */ \
+  UINT f_op1; \
+  UINT f_r1; \
+  UINT f_op2; \
+  UINT f_r2; \
+  unsigned int length;
+#define EXTRACT_FMT_24_JMP_CODE \
+  length = 2; \
+  f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
+  f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
+  f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
+  f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
+
+#define EXTRACT_FMT_25_LD_VARS \
+  /* Instruction fields.  */ \
+  UINT f_op1; \
+  UINT f_r1; \
+  UINT f_op2; \
+  UINT f_r2; \
+  unsigned int length;
+#define EXTRACT_FMT_25_LD_CODE \
+  length = 2; \
+  f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
+  f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
+  f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
+  f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
+
+#define EXTRACT_FMT_26_LD_D_VARS \
+  /* Instruction fields.  */ \
+  UINT f_op1; \
+  UINT f_r1; \
+  UINT f_op2; \
+  UINT f_r2; \
+  int f_simm16; \
+  unsigned int length;
+#define EXTRACT_FMT_26_LD_D_CODE \
+  length = 4; \
+  f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
+  f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
+  f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4); \
+  f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
+  f_simm16 = EXTRACT_SIGNED (insn, 32, 16, 16); \
+
+#define EXTRACT_FMT_27_LDB_VARS \
+  /* Instruction fields.  */ \
+  UINT f_op1; \
+  UINT f_r1; \
+  UINT f_op2; \
+  UINT f_r2; \
+  unsigned int length;
+#define EXTRACT_FMT_27_LDB_CODE \
+  length = 2; \
+  f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
+  f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
+  f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
+  f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
+
+#define EXTRACT_FMT_28_LDB_D_VARS \
+  /* Instruction fields.  */ \
+  UINT f_op1; \
+  UINT f_r1; \
+  UINT f_op2; \
+  UINT f_r2; \
+  int f_simm16; \
+  unsigned int length;
+#define EXTRACT_FMT_28_LDB_D_CODE \
+  length = 4; \
+  f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
+  f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
+  f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4); \
+  f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
+  f_simm16 = EXTRACT_SIGNED (insn, 32, 16, 16); \
+
+#define EXTRACT_FMT_29_LDH_VARS \
+  /* Instruction fields.  */ \
+  UINT f_op1; \
+  UINT f_r1; \
+  UINT f_op2; \
+  UINT f_r2; \
+  unsigned int length;
+#define EXTRACT_FMT_29_LDH_CODE \
+  length = 2; \
+  f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
+  f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
+  f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
+  f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
+
+#define EXTRACT_FMT_30_LDH_D_VARS \
+  /* Instruction fields.  */ \
+  UINT f_op1; \
+  UINT f_r1; \
+  UINT f_op2; \
+  UINT f_r2; \
+  int f_simm16; \
+  unsigned int length;
+#define EXTRACT_FMT_30_LDH_D_CODE \
+  length = 4; \
+  f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
+  f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
+  f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4); \
+  f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
+  f_simm16 = EXTRACT_SIGNED (insn, 32, 16, 16); \
+
+#define EXTRACT_FMT_31_LD24_VARS \
+  /* Instruction fields.  */ \
+  UINT f_op1; \
+  UINT f_r1; \
+  UINT f_uimm24; \
+  unsigned int length;
+#define EXTRACT_FMT_31_LD24_CODE \
+  length = 4; \
+  f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
+  f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
+  f_uimm24 = EXTRACT_UNSIGNED (insn, 32, 8, 24); \
+
+#define EXTRACT_FMT_32_LDI8_VARS \
+  /* Instruction fields.  */ \
+  UINT f_op1; \
+  UINT f_r1; \
+  int f_simm8; \
+  unsigned int length;
+#define EXTRACT_FMT_32_LDI8_CODE \
+  length = 2; \
+  f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
+  f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
+  f_simm8 = EXTRACT_SIGNED (insn, 16, 8, 8); \
+
+#define EXTRACT_FMT_33_LDI16_VARS \
+  /* Instruction fields.  */ \
+  UINT f_op1; \
+  UINT f_r1; \
+  UINT f_op2; \
+  UINT f_r2; \
+  int f_simm16; \
+  unsigned int length;
+#define EXTRACT_FMT_33_LDI16_CODE \
+  length = 4; \
+  f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
+  f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
+  f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4); \
+  f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
+  f_simm16 = EXTRACT_SIGNED (insn, 32, 16, 16); \
+
+#define EXTRACT_FMT_34_MACHI_VARS \
+  /* Instruction fields.  */ \
+  UINT f_op1; \
+  UINT f_r1; \
+  UINT f_op2; \
+  UINT f_r2; \
+  unsigned int length;
+#define EXTRACT_FMT_34_MACHI_CODE \
+  length = 2; \
+  f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
+  f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
+  f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
+  f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
+
+#define EXTRACT_FMT_35_MACHI_A_VARS \
+  /* Instruction fields.  */ \
+  UINT f_op1; \
+  UINT f_r1; \
+  UINT f_acc; \
+  UINT f_op23; \
+  UINT f_r2; \
+  unsigned int length;
+#define EXTRACT_FMT_35_MACHI_A_CODE \
+  length = 2; \
+  f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
+  f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
+  f_acc = EXTRACT_UNSIGNED (insn, 16, 8, 1); \
+  f_op23 = EXTRACT_UNSIGNED (insn, 16, 9, 3); \
+  f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
+
+#define EXTRACT_FMT_36_MULHI_A_VARS \
+  /* Instruction fields.  */ \
+  UINT f_op1; \
+  UINT f_r1; \
+  UINT f_acc; \
+  UINT f_op23; \
+  UINT f_r2; \
+  unsigned int length;
+#define EXTRACT_FMT_36_MULHI_A_CODE \
+  length = 2; \
+  f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
+  f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
+  f_acc = EXTRACT_UNSIGNED (insn, 16, 8, 1); \
+  f_op23 = EXTRACT_UNSIGNED (insn, 16, 9, 3); \
+  f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
+
+#define EXTRACT_FMT_37_MV_VARS \
+  /* Instruction fields.  */ \
+  UINT f_op1; \
+  UINT f_r1; \
+  UINT f_op2; \
+  UINT f_r2; \
+  unsigned int length;
+#define EXTRACT_FMT_37_MV_CODE \
+  length = 2; \
+  f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
+  f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
+  f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
+  f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
+
+#define EXTRACT_FMT_38_MVFACHI_VARS \
+  /* Instruction fields.  */ \
+  UINT f_op1; \
+  UINT f_r1; \
+  UINT f_op2; \
+  UINT f_r2; \
+  unsigned int length;
+#define EXTRACT_FMT_38_MVFACHI_CODE \
+  length = 2; \
+  f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
+  f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
+  f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
+  f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
+
+#define EXTRACT_FMT_39_MVFACHI_A_VARS \
+  /* Instruction fields.  */ \
+  UINT f_op1; \
+  UINT f_r1; \
+  UINT f_op2; \
+  UINT f_accs; \
+  UINT f_op3; \
+  unsigned int length;
+#define EXTRACT_FMT_39_MVFACHI_A_CODE \
+  length = 2; \
+  f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
+  f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
+  f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
+  f_accs = EXTRACT_UNSIGNED (insn, 16, 12, 2); \
+  f_op3 = EXTRACT_UNSIGNED (insn, 16, 14, 2); \
+
+#define EXTRACT_FMT_40_MVFC_VARS \
+  /* Instruction fields.  */ \
+  UINT f_op1; \
+  UINT f_r1; \
+  UINT f_op2; \
+  UINT f_r2; \
+  unsigned int length;
+#define EXTRACT_FMT_40_MVFC_CODE \
+  length = 2; \
+  f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
+  f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
+  f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
+  f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
+
+#define EXTRACT_FMT_41_MVTACHI_VARS \
+  /* Instruction fields.  */ \
+  UINT f_op1; \
+  UINT f_r1; \
+  UINT f_op2; \
+  UINT f_r2; \
+  unsigned int length;
+#define EXTRACT_FMT_41_MVTACHI_CODE \
+  length = 2; \
+  f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
+  f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
+  f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
+  f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
+
+#define EXTRACT_FMT_42_MVTACHI_A_VARS \
+  /* Instruction fields.  */ \
+  UINT f_op1; \
+  UINT f_r1; \
+  UINT f_op2; \
+  UINT f_accs; \
+  UINT f_op3; \
+  unsigned int length;
+#define EXTRACT_FMT_42_MVTACHI_A_CODE \
+  length = 2; \
+  f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
+  f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
+  f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
+  f_accs = EXTRACT_UNSIGNED (insn, 16, 12, 2); \
+  f_op3 = EXTRACT_UNSIGNED (insn, 16, 14, 2); \
+
+#define EXTRACT_FMT_43_MVTC_VARS \
+  /* Instruction fields.  */ \
+  UINT f_op1; \
+  UINT f_r1; \
+  UINT f_op2; \
+  UINT f_r2; \
+  unsigned int length;
+#define EXTRACT_FMT_43_MVTC_CODE \
+  length = 2; \
+  f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
+  f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
+  f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
+  f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
+
+#define EXTRACT_FMT_44_NOP_VARS \
+  /* Instruction fields.  */ \
+  UINT f_op1; \
+  UINT f_r1; \
+  UINT f_op2; \
+  UINT f_r2; \
+  unsigned int length;
+#define EXTRACT_FMT_44_NOP_CODE \
+  length = 2; \
+  f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
+  f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
+  f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
+  f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
+
+#define EXTRACT_FMT_45_RAC_VARS \
+  /* Instruction fields.  */ \
+  UINT f_op1; \
+  UINT f_r1; \
+  UINT f_op2; \
+  UINT f_r2; \
+  unsigned int length;
+#define EXTRACT_FMT_45_RAC_CODE \
+  length = 2; \
+  f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
+  f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
+  f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
+  f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
+
+#define EXTRACT_FMT_46_RAC_A_VARS \
+  /* Instruction fields.  */ \
+  UINT f_op1; \
+  UINT f_r1; \
+  UINT f_op2; \
+  UINT f_accs; \
+  UINT f_op3; \
+  unsigned int length;
+#define EXTRACT_FMT_46_RAC_A_CODE \
+  length = 2; \
+  f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
+  f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
+  f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
+  f_accs = EXTRACT_UNSIGNED (insn, 16, 12, 2); \
+  f_op3 = EXTRACT_UNSIGNED (insn, 16, 14, 2); \
+
+#define EXTRACT_FMT_47_SETH_VARS \
+  /* Instruction fields.  */ \
+  UINT f_op1; \
+  UINT f_r1; \
+  UINT f_op2; \
+  UINT f_r2; \
+  UINT f_hi16; \
+  unsigned int length;
+#define EXTRACT_FMT_47_SETH_CODE \
+  length = 4; \
+  f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
+  f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
+  f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4); \
+  f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
+  f_hi16 = EXTRACT_UNSIGNED (insn, 32, 16, 16); \
+
+#define EXTRACT_FMT_48_SLLI_VARS \
+  /* Instruction fields.  */ \
+  UINT f_op1; \
+  UINT f_r1; \
+  UINT f_shift_op2; \
+  UINT f_uimm5; \
+  unsigned int length;
+#define EXTRACT_FMT_48_SLLI_CODE \
+  length = 2; \
+  f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
+  f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
+  f_shift_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 3); \
+  f_uimm5 = EXTRACT_UNSIGNED (insn, 16, 11, 5); \
+
+#define EXTRACT_FMT_49_ST_D_VARS \
+  /* Instruction fields.  */ \
+  UINT f_op1; \
+  UINT f_r1; \
+  UINT f_op2; \
+  UINT f_r2; \
+  int f_simm16; \
+  unsigned int length;
+#define EXTRACT_FMT_49_ST_D_CODE \
+  length = 4; \
+  f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
+  f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
+  f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4); \
+  f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
+  f_simm16 = EXTRACT_SIGNED (insn, 32, 16, 16); \
+
+#define EXTRACT_FMT_50_TRAP_VARS \
+  /* Instruction fields.  */ \
+  UINT f_op1; \
+  UINT f_r1; \
+  UINT f_op2; \
+  UINT f_uimm4; \
+  unsigned int length;
+#define EXTRACT_FMT_50_TRAP_CODE \
+  length = 2; \
+  f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
+  f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
+  f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
+  f_uimm4 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
+
+#define EXTRACT_FMT_51_SATB_VARS \
+  /* Instruction fields.  */ \
+  UINT f_op1; \
+  UINT f_r1; \
+  UINT f_op2; \
+  UINT f_r2; \
+  UINT f_uimm16; \
+  unsigned int length;
+#define EXTRACT_FMT_51_SATB_CODE \
+  length = 4; \
+  f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
+  f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
+  f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4); \
+  f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
+  f_uimm16 = EXTRACT_UNSIGNED (insn, 32, 16, 16); \
+
+#define EXTRACT_FMT_52_PCMPBZ_VARS \
+  /* Instruction fields.  */ \
+  UINT f_op1; \
+  UINT f_r1; \
+  UINT f_op2; \
+  UINT f_r2; \
+  unsigned int length;
+#define EXTRACT_FMT_52_PCMPBZ_CODE \
+  length = 2; \
+  f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
+  f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
+  f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
+  f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
+
+#define EXTRACT_FMT_53_SADD_VARS \
+  /* Instruction fields.  */ \
+  UINT f_op1; \
+  UINT f_r1; \
+  UINT f_op2; \
+  UINT f_r2; \
+  unsigned int length;
+#define EXTRACT_FMT_53_SADD_CODE \
+  length = 2; \
+  f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
+  f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
+  f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
+  f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
+
+#define EXTRACT_FMT_54_MACWU1_VARS \
+  /* Instruction fields.  */ \
+  UINT f_op1; \
+  UINT f_r1; \
+  UINT f_op2; \
+  UINT f_r2; \
+  unsigned int length;
+#define EXTRACT_FMT_54_MACWU1_CODE \
+  length = 2; \
+  f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
+  f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
+  f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
+  f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
+
+#define EXTRACT_FMT_55_SC_VARS \
+  /* Instruction fields.  */ \
+  UINT f_op1; \
+  UINT f_r1; \
+  UINT f_op2; \
+  UINT f_r2; \
+  unsigned int length;
+#define EXTRACT_FMT_55_SC_CODE \
+  length = 2; \
+  f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
+  f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
+  f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
+  f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
+
+/* Fetched input values of an instruction.  */
+
+struct parallel_exec {
+  union {
+    struct { /* e.g. add $dr,$sr */
+      SI dr;
+      SI sr;
+    } fmt_0_add;
+    struct { /* e.g. add3 $dr,$sr,#$slo16 */
+      HI slo16;
+      SI sr;
+    } fmt_1_add3;
+    struct { /* e.g. and3 $dr,$sr,#$uimm16 */
+      SI sr;
+      USI uimm16;
+    } fmt_2_and3;
+    struct { /* e.g. or3 $dr,$sr,#$ulo16 */
+      SI sr;
+      UHI ulo16;
+    } fmt_3_or3;
+    struct { /* e.g. addi $dr,#$simm8 */
+      SI dr;
+      SI simm8;
+    } fmt_4_addi;
+    struct { /* e.g. addv3 $dr,$sr,#$simm16 */
+      SI simm16;
+      SI sr;
+    } fmt_5_addv3;
+    struct { /* e.g. addx $dr,$sr */
+      UBI condbit;
+      SI dr;
+      SI sr;
+    } fmt_6_addx;
+    struct { /* e.g. bc $disp8 */
+      UBI condbit;
+      IADDR disp8;
+    } fmt_7_bc8;
+    struct { /* e.g. bc $disp24 */
+      UBI condbit;
+      IADDR disp24;
+    } fmt_8_bc24;
+    struct { /* e.g. beq $src1,$src2,$disp16 */
+      IADDR disp16;
+      SI src1;
+      SI src2;
+    } fmt_9_beq;
+    struct { /* e.g. beqz $src2,$disp16 */
+      IADDR disp16;
+      SI src2;
+    } fmt_10_beqz;
+    struct { /* e.g. bl $disp8 */
+      IADDR disp8;
+      USI pc;
+    } fmt_11_bl8;
+    struct { /* e.g. bl $disp24 */
+      IADDR disp24;
+      USI pc;
+    } fmt_12_bl24;
+    struct { /* e.g. bcl $disp8 */
+      UBI condbit;
+      IADDR disp8;
+      USI pc;
+    } fmt_13_bcl8;
+    struct { /* e.g. bcl $disp24 */
+      UBI condbit;
+      IADDR disp24;
+      USI pc;
+    } fmt_14_bcl24;
+    struct { /* e.g. bra $disp8 */
+      IADDR disp8;
+    } fmt_15_bra8;
+    struct { /* e.g. bra $disp24 */
+      IADDR disp24;
+    } fmt_16_bra24;
+    struct { /* e.g. cmp $src1,$src2 */
+      SI src1;
+      SI src2;
+    } fmt_17_cmp;
+    struct { /* e.g. cmpi $src2,#$simm16 */
+      SI simm16;
+      SI src2;
+    } fmt_18_cmpi;
+    struct { /* e.g. cmpui $src2,#$uimm16 */
+      SI src2;
+      USI uimm16;
+    } fmt_19_cmpui;
+    struct { /* e.g. cmpz $src2 */
+      SI src2;
+    } fmt_20_cmpz;
+    struct { /* e.g. div $dr,$sr */
+      SI dr;
+      SI sr;
+    } fmt_21_div;
+    struct { /* e.g. jc $sr */
+      UBI condbit;
+      SI sr;
+    } fmt_22_jc;
+    struct { /* e.g. jl $sr */
+      USI pc;
+      SI sr;
+    } fmt_23_jl;
+    struct { /* e.g. jmp $sr */
+      SI sr;
+    } fmt_24_jmp;
+    struct { /* e.g. ld $dr,@$sr */
+      UQI h_memory;
+      SI sr;
+    } fmt_25_ld;
+    struct { /* e.g. ld $dr,@($slo16,$sr) */
+      UQI h_memory;
+      HI slo16;
+      SI sr;
+    } fmt_26_ld_d;
+    struct { /* e.g. ldb $dr,@$sr */
+      UQI h_memory;
+      SI sr;
+    } fmt_27_ldb;
+    struct { /* e.g. ldb $dr,@($slo16,$sr) */
+      UQI h_memory;
+      HI slo16;
+      SI sr;
+    } fmt_28_ldb_d;
+    struct { /* e.g. ldh $dr,@$sr */
+      UQI h_memory;
+      SI sr;
+    } fmt_29_ldh;
+    struct { /* e.g. ldh $dr,@($slo16,$sr) */
+      UQI h_memory;
+      HI slo16;
+      SI sr;
+    } fmt_30_ldh_d;
+    struct { /* e.g. ld24 $dr,#$uimm24 */
+      ADDR uimm24;
+    } fmt_31_ld24;
+    struct { /* e.g. ldi $dr,#$simm8 */
+      SI simm8;
+    } fmt_32_ldi8;
+    struct { /* e.g. ldi $dr,$slo16 */
+      HI slo16;
+    } fmt_33_ldi16;
+    struct { /* e.g. machi $src1,$src2 */
+      DI accum;
+      SI src1;
+      SI src2;
+    } fmt_34_machi;
+    struct { /* e.g. machi $src1,$src2,$acc */
+      DI acc;
+      SI src1;
+      SI src2;
+    } fmt_35_machi_a;
+    struct { /* e.g. mulhi $src1,$src2,$acc */
+      SI src1;
+      SI src2;
+    } fmt_36_mulhi_a;
+    struct { /* e.g. mv $dr,$sr */
+      SI sr;
+    } fmt_37_mv;
+    struct { /* e.g. mvfachi $dr */
+      DI accum;
+    } fmt_38_mvfachi;
+    struct { /* e.g. mvfachi $dr,$accs */
+      DI accs;
+    } fmt_39_mvfachi_a;
+    struct { /* e.g. mvfc $dr,$scr */
+      SI scr;
+    } fmt_40_mvfc;
+    struct { /* e.g. mvtachi $src1 */
+      DI accum;
+      SI src1;
+    } fmt_41_mvtachi;
+    struct { /* e.g. mvtachi $src1,$accs */
+      DI accs;
+      SI src1;
+    } fmt_42_mvtachi_a;
+    struct { /* e.g. mvtc $sr,$dcr */
+      SI sr;
+    } fmt_43_mvtc;
+    struct { /* e.g. nop */
+      int empty;
+    } fmt_44_nop;
+    struct { /* e.g. rac */
+      DI accum;
+    } fmt_45_rac;
+    struct { /* e.g. rac $accs */
+      DI accs;
+    } fmt_46_rac_a;
+    struct { /* e.g. seth $dr,$hi16 */
+      UHI hi16;
+    } fmt_47_seth;
+    struct { /* e.g. slli $dr,#$uimm5 */
+      SI dr;
+      USI uimm5;
+    } fmt_48_slli;
+    struct { /* e.g. st $src1,@($slo16,$src2) */
+      HI slo16;
+      SI src1;
+      SI src2;
+    } fmt_49_st_d;
+    struct { /* e.g. trap #$uimm4 */
+      USI uimm4;
+    } fmt_50_trap;
+    struct { /* e.g. satb $dr,$src2 */
+      int empty;
+    } fmt_51_satb;
+    struct { /* e.g. pcmpbz $src2 */
+      int empty;
+    } fmt_52_pcmpbz;
+    struct { /* e.g. sadd */
+      DI h_accums;
+      DI h_accums;
+    } fmt_53_sadd;
+    struct { /* e.g. macwu1 $src1,$src2 */
+      DI h_accums;
+      SI src1;
+      SI src2;
+    } fmt_54_macwu1;
+    struct { /* e.g. sc */
+      UBI condbit;
+    } fmt_55_sc;
+  } operands;
+};
+
+#endif /* CPU_M32RX_H */
diff --git a/sim/m32r/readx.c b/sim/m32r/readx.c
new file mode 100644
index 00000000000..3b796380bad
--- /dev/null
+++ b/sim/m32r/readx.c
@@ -0,0 +1,896 @@
+/* Simulator instruction operand reader for m32r.
+
+Copyright (C) 1996, 1997, 1998 Free Software Foundation, Inc.
+
+This file is part of the GNU Simulators.
+
+This program is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2, or (at your option)
+any later version.
+
+This program is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License along
+with this program; if not, write to the Free Software Foundation, Inc.,
+59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+
+*/
+
+#define WANT_CPU
+#define WANT_CPU_M32RX
+
+#include "sim-main.h"
+#include "cpu-sim.h"
+
+#ifdef DEFINE_LABELS
+#undef DEFINE_LABELS
+
+
+  /* The labels have the case they have because the enum of insn types
+     is all uppercase and in the non-stdc case the fmt symbol is built
+     into the enum name.
+
+     The order here must match the order in m32rx_decode_vars in decode.c.  */
+
+  static void *labels[] = {
+    && case_read_READ_ILLEGAL,
+    && case_read_READ_FMT_0_ADD,
+    && case_read_READ_FMT_1_ADD3,
+    && case_read_READ_FMT_2_AND3,
+    && case_read_READ_FMT_3_OR3,
+    && case_read_READ_FMT_4_ADDI,
+    && case_read_READ_FMT_5_ADDV3,
+    && case_read_READ_FMT_6_ADDX,
+    && case_read_READ_FMT_7_BC8,
+    && case_read_READ_FMT_8_BC24,
+    && case_read_READ_FMT_9_BEQ,
+    && case_read_READ_FMT_10_BEQZ,
+    && case_read_READ_FMT_11_BL8,
+    && case_read_READ_FMT_12_BL24,
+    && case_read_READ_FMT_13_BCL8,
+    && case_read_READ_FMT_14_BCL24,
+    && case_read_READ_FMT_15_BRA8,
+    && case_read_READ_FMT_16_BRA24,
+    && case_read_READ_FMT_17_CMP,
+    && case_read_READ_FMT_18_CMPI,
+    && case_read_READ_FMT_19_CMPUI,
+    && case_read_READ_FMT_20_CMPZ,
+    && case_read_READ_FMT_21_DIV,
+    && case_read_READ_FMT_22_JC,
+    && case_read_READ_FMT_23_JL,
+    && case_read_READ_FMT_24_JMP,
+    && case_read_READ_FMT_25_LD,
+    && case_read_READ_FMT_26_LD_D,
+    && case_read_READ_FMT_27_LDB,
+    && case_read_READ_FMT_28_LDB_D,
+    && case_read_READ_FMT_29_LDH,
+    && case_read_READ_FMT_30_LDH_D,
+    && case_read_READ_FMT_31_LD24,
+    && case_read_READ_FMT_32_LDI8,
+    && case_read_READ_FMT_33_LDI16,
+    && case_read_READ_FMT_34_MACHI,
+    && case_read_READ_FMT_35_MACHI_A,
+    && case_read_READ_FMT_36_MULHI_A,
+    && case_read_READ_FMT_37_MV,
+    && case_read_READ_FMT_38_MVFACHI,
+    && case_read_READ_FMT_39_MVFACHI_A,
+    && case_read_READ_FMT_40_MVFC,
+    && case_read_READ_FMT_41_MVTACHI,
+    && case_read_READ_FMT_42_MVTACHI_A,
+    && case_read_READ_FMT_43_MVTC,
+    && case_read_READ_FMT_44_NOP,
+    && case_read_READ_FMT_45_RAC,
+    && case_read_READ_FMT_46_RAC_A,
+    && case_read_READ_FMT_47_SETH,
+    && case_read_READ_FMT_48_SLLI,
+    && case_read_READ_FMT_49_ST_D,
+    && case_read_READ_FMT_50_TRAP,
+    && case_read_READ_FMT_51_SATB,
+    && case_read_READ_FMT_52_PCMPBZ,
+    && case_read_READ_FMT_53_SADD,
+    && case_read_READ_FMT_54_MACWU1,
+    && case_read_READ_FMT_55_SC,
+    0
+  };
+  extern DECODE *m32rx_decode_vars[];
+  int i;
+
+  for (i = 0; m32rx_decode_vars[i] != 0; ++i)
+    m32rx_decode_vars[i]->read = labels[i];
+
+#endif /* DEFINE_LABELS */
+
+#ifdef DEFINE_SWITCH
+#undef DEFINE_SWITCH
+
+{
+  SWITCH (read, decode->read)
+    {
+
+    CASE (read, READ_ILLEGAL) :
+    {
+      sim_engine_illegal_insn (current_cpu, NULL_CIA /*FIXME*/);
+    }
+    BREAK (read);
+
+    CASE (read, READ_FMT_0_ADD) : /* e.g. add $dr,$sr */
+    {
+#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_0_add.f
+  EXTRACT_FMT_0_ADD_VARS /* f-op1 f-r1 f-op2 f-r2 */
+
+  EXTRACT_FMT_0_ADD_CODE
+
+      /* Fetch the input operands for the semantic handler.  */
+      OPRND (dr) = CPU (h_gr[f_r1]);
+      OPRND (sr) = CPU (h_gr[f_r2]);
+#undef OPRND
+    }
+    BREAK (read);
+
+    CASE (read, READ_FMT_1_ADD3) : /* e.g. add3 $dr,$sr,#$slo16 */
+    {
+#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_1_add3.f
+  EXTRACT_FMT_1_ADD3_VARS /* f-op1 f-r1 f-op2 f-r2 f-simm16 */
+
+  EXTRACT_FMT_1_ADD3_CODE
+
+      /* Fetch the input operands for the semantic handler.  */
+      OPRND (slo16) = f_simm16;
+      OPRND (sr) = CPU (h_gr[f_r2]);
+#undef OPRND
+    }
+    BREAK (read);
+
+    CASE (read, READ_FMT_2_AND3) : /* e.g. and3 $dr,$sr,#$uimm16 */
+    {
+#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_2_and3.f
+  EXTRACT_FMT_2_AND3_VARS /* f-op1 f-r1 f-op2 f-r2 f-uimm16 */
+
+  EXTRACT_FMT_2_AND3_CODE
+
+      /* Fetch the input operands for the semantic handler.  */
+      OPRND (sr) = CPU (h_gr[f_r2]);
+      OPRND (uimm16) = f_uimm16;
+#undef OPRND
+    }
+    BREAK (read);
+
+    CASE (read, READ_FMT_3_OR3) : /* e.g. or3 $dr,$sr,#$ulo16 */
+    {
+#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_3_or3.f
+  EXTRACT_FMT_3_OR3_VARS /* f-op1 f-r1 f-op2 f-r2 f-uimm16 */
+
+  EXTRACT_FMT_3_OR3_CODE
+
+      /* Fetch the input operands for the semantic handler.  */
+      OPRND (sr) = CPU (h_gr[f_r2]);
+      OPRND (ulo16) = f_uimm16;
+#undef OPRND
+    }
+    BREAK (read);
+
+    CASE (read, READ_FMT_4_ADDI) : /* e.g. addi $dr,#$simm8 */
+    {
+#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_4_addi.f
+  EXTRACT_FMT_4_ADDI_VARS /* f-op1 f-r1 f-simm8 */
+
+  EXTRACT_FMT_4_ADDI_CODE
+
+      /* Fetch the input operands for the semantic handler.  */
+      OPRND (dr) = CPU (h_gr[f_r1]);
+      OPRND (simm8) = f_simm8;
+#undef OPRND
+    }
+    BREAK (read);
+
+    CASE (read, READ_FMT_5_ADDV3) : /* e.g. addv3 $dr,$sr,#$simm16 */
+    {
+#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_5_addv3.f
+  EXTRACT_FMT_5_ADDV3_VARS /* f-op1 f-r1 f-op2 f-r2 f-simm16 */
+
+  EXTRACT_FMT_5_ADDV3_CODE
+
+      /* Fetch the input operands for the semantic handler.  */
+      OPRND (simm16) = f_simm16;
+      OPRND (sr) = CPU (h_gr[f_r2]);
+#undef OPRND
+    }
+    BREAK (read);
+
+    CASE (read, READ_FMT_6_ADDX) : /* e.g. addx $dr,$sr */
+    {
+#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_6_addx.f
+  EXTRACT_FMT_6_ADDX_VARS /* f-op1 f-r1 f-op2 f-r2 */
+
+  EXTRACT_FMT_6_ADDX_CODE
+
+      /* Fetch the input operands for the semantic handler.  */
+      OPRND (condbit) = CPU (h_cond);
+      OPRND (dr) = CPU (h_gr[f_r1]);
+      OPRND (sr) = CPU (h_gr[f_r2]);
+#undef OPRND
+    }
+    BREAK (read);
+
+    CASE (read, READ_FMT_7_BC8) : /* e.g. bc $disp8 */
+    {
+#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_7_bc8.f
+  EXTRACT_FMT_7_BC8_VARS /* f-op1 f-r1 f-disp8 */
+
+  EXTRACT_FMT_7_BC8_CODE
+
+      /* Fetch the input operands for the semantic handler.  */
+      OPRND (condbit) = CPU (h_cond);
+      OPRND (disp8) = f_disp8;
+#undef OPRND
+    }
+    BREAK (read);
+
+    CASE (read, READ_FMT_8_BC24) : /* e.g. bc $disp24 */
+    {
+#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_8_bc24.f
+  EXTRACT_FMT_8_BC24_VARS /* f-op1 f-r1 f-disp24 */
+
+  EXTRACT_FMT_8_BC24_CODE
+
+      /* Fetch the input operands for the semantic handler.  */
+      OPRND (condbit) = CPU (h_cond);
+      OPRND (disp24) = f_disp24;
+#undef OPRND
+    }
+    BREAK (read);
+
+    CASE (read, READ_FMT_9_BEQ) : /* e.g. beq $src1,$src2,$disp16 */
+    {
+#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_9_beq.f
+  EXTRACT_FMT_9_BEQ_VARS /* f-op1 f-r1 f-op2 f-r2 f-disp16 */
+
+  EXTRACT_FMT_9_BEQ_CODE
+
+      /* Fetch the input operands for the semantic handler.  */
+      OPRND (disp16) = f_disp16;
+      OPRND (src1) = CPU (h_gr[f_r1]);
+      OPRND (src2) = CPU (h_gr[f_r2]);
+#undef OPRND
+    }
+    BREAK (read);
+
+    CASE (read, READ_FMT_10_BEQZ) : /* e.g. beqz $src2,$disp16 */
+    {
+#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_10_beqz.f
+  EXTRACT_FMT_10_BEQZ_VARS /* f-op1 f-r1 f-op2 f-r2 f-disp16 */
+
+  EXTRACT_FMT_10_BEQZ_CODE
+
+      /* Fetch the input operands for the semantic handler.  */
+      OPRND (disp16) = f_disp16;
+      OPRND (src2) = CPU (h_gr[f_r2]);
+#undef OPRND
+    }
+    BREAK (read);
+
+    CASE (read, READ_FMT_11_BL8) : /* e.g. bl $disp8 */
+    {
+#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_11_bl8.f
+  EXTRACT_FMT_11_BL8_VARS /* f-op1 f-r1 f-disp8 */
+
+  EXTRACT_FMT_11_BL8_CODE
+
+      /* Fetch the input operands for the semantic handler.  */
+      OPRND (disp8) = f_disp8;
+      OPRND (pc) = CPU (h_pc);
+#undef OPRND
+    }
+    BREAK (read);
+
+    CASE (read, READ_FMT_12_BL24) : /* e.g. bl $disp24 */
+    {
+#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_12_bl24.f
+  EXTRACT_FMT_12_BL24_VARS /* f-op1 f-r1 f-disp24 */
+
+  EXTRACT_FMT_12_BL24_CODE
+
+      /* Fetch the input operands for the semantic handler.  */
+      OPRND (disp24) = f_disp24;
+      OPRND (pc) = CPU (h_pc);
+#undef OPRND
+    }
+    BREAK (read);
+
+    CASE (read, READ_FMT_13_BCL8) : /* e.g. bcl $disp8 */
+    {
+#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_13_bcl8.f
+  EXTRACT_FMT_13_BCL8_VARS /* f-op1 f-r1 f-disp8 */
+
+  EXTRACT_FMT_13_BCL8_CODE
+
+      /* Fetch the input operands for the semantic handler.  */
+      OPRND (condbit) = CPU (h_cond);
+      OPRND (disp8) = f_disp8;
+      OPRND (pc) = CPU (h_pc);
+#undef OPRND
+    }
+    BREAK (read);
+
+    CASE (read, READ_FMT_14_BCL24) : /* e.g. bcl $disp24 */
+    {
+#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_14_bcl24.f
+  EXTRACT_FMT_14_BCL24_VARS /* f-op1 f-r1 f-disp24 */
+
+  EXTRACT_FMT_14_BCL24_CODE
+
+      /* Fetch the input operands for the semantic handler.  */
+      OPRND (condbit) = CPU (h_cond);
+      OPRND (disp24) = f_disp24;
+      OPRND (pc) = CPU (h_pc);
+#undef OPRND
+    }
+    BREAK (read);
+
+    CASE (read, READ_FMT_15_BRA8) : /* e.g. bra $disp8 */
+    {
+#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_15_bra8.f
+  EXTRACT_FMT_15_BRA8_VARS /* f-op1 f-r1 f-disp8 */
+
+  EXTRACT_FMT_15_BRA8_CODE
+
+      /* Fetch the input operands for the semantic handler.  */
+      OPRND (disp8) = f_disp8;
+#undef OPRND
+    }
+    BREAK (read);
+
+    CASE (read, READ_FMT_16_BRA24) : /* e.g. bra $disp24 */
+    {
+#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_16_bra24.f
+  EXTRACT_FMT_16_BRA24_VARS /* f-op1 f-r1 f-disp24 */
+
+  EXTRACT_FMT_16_BRA24_CODE
+
+      /* Fetch the input operands for the semantic handler.  */
+      OPRND (disp24) = f_disp24;
+#undef OPRND
+    }
+    BREAK (read);
+
+    CASE (read, READ_FMT_17_CMP) : /* e.g. cmp $src1,$src2 */
+    {
+#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_17_cmp.f
+  EXTRACT_FMT_17_CMP_VARS /* f-op1 f-r1 f-op2 f-r2 */
+
+  EXTRACT_FMT_17_CMP_CODE
+
+      /* Fetch the input operands for the semantic handler.  */
+      OPRND (src1) = CPU (h_gr[f_r1]);
+      OPRND (src2) = CPU (h_gr[f_r2]);
+#undef OPRND
+    }
+    BREAK (read);
+
+    CASE (read, READ_FMT_18_CMPI) : /* e.g. cmpi $src2,#$simm16 */
+    {
+#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_18_cmpi.f
+  EXTRACT_FMT_18_CMPI_VARS /* f-op1 f-r1 f-op2 f-r2 f-simm16 */
+
+  EXTRACT_FMT_18_CMPI_CODE
+
+      /* Fetch the input operands for the semantic handler.  */
+      OPRND (simm16) = f_simm16;
+      OPRND (src2) = CPU (h_gr[f_r2]);
+#undef OPRND
+    }
+    BREAK (read);
+
+    CASE (read, READ_FMT_19_CMPUI) : /* e.g. cmpui $src2,#$uimm16 */
+    {
+#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_19_cmpui.f
+  EXTRACT_FMT_19_CMPUI_VARS /* f-op1 f-r1 f-op2 f-r2 f-uimm16 */
+
+  EXTRACT_FMT_19_CMPUI_CODE
+
+      /* Fetch the input operands for the semantic handler.  */
+      OPRND (src2) = CPU (h_gr[f_r2]);
+      OPRND (uimm16) = f_uimm16;
+#undef OPRND
+    }
+    BREAK (read);
+
+    CASE (read, READ_FMT_20_CMPZ) : /* e.g. cmpz $src2 */
+    {
+#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_20_cmpz.f
+  EXTRACT_FMT_20_CMPZ_VARS /* f-op1 f-r1 f-op2 f-r2 */
+
+  EXTRACT_FMT_20_CMPZ_CODE
+
+      /* Fetch the input operands for the semantic handler.  */
+      OPRND (src2) = CPU (h_gr[f_r2]);
+#undef OPRND
+    }
+    BREAK (read);
+
+    CASE (read, READ_FMT_21_DIV) : /* e.g. div $dr,$sr */
+    {
+#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_21_div.f
+  EXTRACT_FMT_21_DIV_VARS /* f-op1 f-r1 f-op2 f-r2 f-simm16 */
+
+  EXTRACT_FMT_21_DIV_CODE
+
+      /* Fetch the input operands for the semantic handler.  */
+      OPRND (dr) = CPU (h_gr[f_r1]);
+      OPRND (sr) = CPU (h_gr[f_r2]);
+#undef OPRND
+    }
+    BREAK (read);
+
+    CASE (read, READ_FMT_22_JC) : /* e.g. jc $sr */
+    {
+#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_22_jc.f
+  EXTRACT_FMT_22_JC_VARS /* f-op1 f-r1 f-op2 f-r2 */
+
+  EXTRACT_FMT_22_JC_CODE
+
+      /* Fetch the input operands for the semantic handler.  */
+      OPRND (condbit) = CPU (h_cond);
+      OPRND (sr) = CPU (h_gr[f_r2]);
+#undef OPRND
+    }
+    BREAK (read);
+
+    CASE (read, READ_FMT_23_JL) : /* e.g. jl $sr */
+    {
+#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_23_jl.f
+  EXTRACT_FMT_23_JL_VARS /* f-op1 f-r1 f-op2 f-r2 */
+
+  EXTRACT_FMT_23_JL_CODE
+
+      /* Fetch the input operands for the semantic handler.  */
+      OPRND (pc) = CPU (h_pc);
+      OPRND (sr) = CPU (h_gr[f_r2]);
+#undef OPRND
+    }
+    BREAK (read);
+
+    CASE (read, READ_FMT_24_JMP) : /* e.g. jmp $sr */
+    {
+#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_24_jmp.f
+  EXTRACT_FMT_24_JMP_VARS /* f-op1 f-r1 f-op2 f-r2 */
+
+  EXTRACT_FMT_24_JMP_CODE
+
+      /* Fetch the input operands for the semantic handler.  */
+      OPRND (sr) = CPU (h_gr[f_r2]);
+#undef OPRND
+    }
+    BREAK (read);
+
+    CASE (read, READ_FMT_25_LD) : /* e.g. ld $dr,@$sr */
+    {
+#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_25_ld.f
+  EXTRACT_FMT_25_LD_VARS /* f-op1 f-r1 f-op2 f-r2 */
+
+  EXTRACT_FMT_25_LD_CODE
+
+      /* Fetch the input operands for the semantic handler.  */
+      OPRND (h_memory) = GETMEMSI (current_cpu, CPU (h_gr[f_r2]));
+      OPRND (sr) = CPU (h_gr[f_r2]);
+#undef OPRND
+    }
+    BREAK (read);
+
+    CASE (read, READ_FMT_26_LD_D) : /* e.g. ld $dr,@($slo16,$sr) */
+    {
+#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_26_ld_d.f
+  EXTRACT_FMT_26_LD_D_VARS /* f-op1 f-r1 f-op2 f-r2 f-simm16 */
+
+  EXTRACT_FMT_26_LD_D_CODE
+
+      /* Fetch the input operands for the semantic handler.  */
+      OPRND (h_memory) = GETMEMSI (current_cpu, ADDSI (CPU (h_gr[f_r2]), f_simm16));
+      OPRND (slo16) = f_simm16;
+      OPRND (sr) = CPU (h_gr[f_r2]);
+#undef OPRND
+    }
+    BREAK (read);
+
+    CASE (read, READ_FMT_27_LDB) : /* e.g. ldb $dr,@$sr */
+    {
+#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_27_ldb.f
+  EXTRACT_FMT_27_LDB_VARS /* f-op1 f-r1 f-op2 f-r2 */
+
+  EXTRACT_FMT_27_LDB_CODE
+
+      /* Fetch the input operands for the semantic handler.  */
+      OPRND (h_memory) = GETMEMQI (current_cpu, CPU (h_gr[f_r2]));
+      OPRND (sr) = CPU (h_gr[f_r2]);
+#undef OPRND
+    }
+    BREAK (read);
+
+    CASE (read, READ_FMT_28_LDB_D) : /* e.g. ldb $dr,@($slo16,$sr) */
+    {
+#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_28_ldb_d.f
+  EXTRACT_FMT_28_LDB_D_VARS /* f-op1 f-r1 f-op2 f-r2 f-simm16 */
+
+  EXTRACT_FMT_28_LDB_D_CODE
+
+      /* Fetch the input operands for the semantic handler.  */
+      OPRND (h_memory) = GETMEMQI (current_cpu, ADDSI (CPU (h_gr[f_r2]), f_simm16));
+      OPRND (slo16) = f_simm16;
+      OPRND (sr) = CPU (h_gr[f_r2]);
+#undef OPRND
+    }
+    BREAK (read);
+
+    CASE (read, READ_FMT_29_LDH) : /* e.g. ldh $dr,@$sr */
+    {
+#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_29_ldh.f
+  EXTRACT_FMT_29_LDH_VARS /* f-op1 f-r1 f-op2 f-r2 */
+
+  EXTRACT_FMT_29_LDH_CODE
+
+      /* Fetch the input operands for the semantic handler.  */
+      OPRND (h_memory) = GETMEMHI (current_cpu, CPU (h_gr[f_r2]));
+      OPRND (sr) = CPU (h_gr[f_r2]);
+#undef OPRND
+    }
+    BREAK (read);
+
+    CASE (read, READ_FMT_30_LDH_D) : /* e.g. ldh $dr,@($slo16,$sr) */
+    {
+#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_30_ldh_d.f
+  EXTRACT_FMT_30_LDH_D_VARS /* f-op1 f-r1 f-op2 f-r2 f-simm16 */
+
+  EXTRACT_FMT_30_LDH_D_CODE
+
+      /* Fetch the input operands for the semantic handler.  */
+      OPRND (h_memory) = GETMEMHI (current_cpu, ADDSI (CPU (h_gr[f_r2]), f_simm16));
+      OPRND (slo16) = f_simm16;
+      OPRND (sr) = CPU (h_gr[f_r2]);
+#undef OPRND
+    }
+    BREAK (read);
+
+    CASE (read, READ_FMT_31_LD24) : /* e.g. ld24 $dr,#$uimm24 */
+    {
+#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_31_ld24.f
+  EXTRACT_FMT_31_LD24_VARS /* f-op1 f-r1 f-uimm24 */
+
+  EXTRACT_FMT_31_LD24_CODE
+
+      /* Fetch the input operands for the semantic handler.  */
+      OPRND (uimm24) = f_uimm24;
+#undef OPRND
+    }
+    BREAK (read);
+
+    CASE (read, READ_FMT_32_LDI8) : /* e.g. ldi $dr,#$simm8 */
+    {
+#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_32_ldi8.f
+  EXTRACT_FMT_32_LDI8_VARS /* f-op1 f-r1 f-simm8 */
+
+  EXTRACT_FMT_32_LDI8_CODE
+
+      /* Fetch the input operands for the semantic handler.  */
+      OPRND (simm8) = f_simm8;
+#undef OPRND
+    }
+    BREAK (read);
+
+    CASE (read, READ_FMT_33_LDI16) : /* e.g. ldi $dr,$slo16 */
+    {
+#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_33_ldi16.f
+  EXTRACT_FMT_33_LDI16_VARS /* f-op1 f-r1 f-op2 f-r2 f-simm16 */
+
+  EXTRACT_FMT_33_LDI16_CODE
+
+      /* Fetch the input operands for the semantic handler.  */
+      OPRND (slo16) = f_simm16;
+#undef OPRND
+    }
+    BREAK (read);
+
+    CASE (read, READ_FMT_34_MACHI) : /* e.g. machi $src1,$src2 */
+    {
+#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_34_machi.f
+  EXTRACT_FMT_34_MACHI_VARS /* f-op1 f-r1 f-op2 f-r2 */
+
+  EXTRACT_FMT_34_MACHI_CODE
+
+      /* Fetch the input operands for the semantic handler.  */
+      OPRND (accum) = CPU (h_accum);
+      OPRND (src1) = CPU (h_gr[f_r1]);
+      OPRND (src2) = CPU (h_gr[f_r2]);
+#undef OPRND
+    }
+    BREAK (read);
+
+    CASE (read, READ_FMT_35_MACHI_A) : /* e.g. machi $src1,$src2,$acc */
+    {
+#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_35_machi_a.f
+  EXTRACT_FMT_35_MACHI_A_VARS /* f-op1 f-r1 f-acc f-op23 f-r2 */
+
+  EXTRACT_FMT_35_MACHI_A_CODE
+
+      /* Fetch the input operands for the semantic handler.  */
+      OPRND (acc) = m32rx_h_accums_get (current_cpu, f_acc);
+      OPRND (src1) = CPU (h_gr[f_r1]);
+      OPRND (src2) = CPU (h_gr[f_r2]);
+#undef OPRND
+    }
+    BREAK (read);
+
+    CASE (read, READ_FMT_36_MULHI_A) : /* e.g. mulhi $src1,$src2,$acc */
+    {
+#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_36_mulhi_a.f
+  EXTRACT_FMT_36_MULHI_A_VARS /* f-op1 f-r1 f-acc f-op23 f-r2 */
+
+  EXTRACT_FMT_36_MULHI_A_CODE
+
+      /* Fetch the input operands for the semantic handler.  */
+      OPRND (src1) = CPU (h_gr[f_r1]);
+      OPRND (src2) = CPU (h_gr[f_r2]);
+#undef OPRND
+    }
+    BREAK (read);
+
+    CASE (read, READ_FMT_37_MV) : /* e.g. mv $dr,$sr */
+    {
+#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_37_mv.f
+  EXTRACT_FMT_37_MV_VARS /* f-op1 f-r1 f-op2 f-r2 */
+
+  EXTRACT_FMT_37_MV_CODE
+
+      /* Fetch the input operands for the semantic handler.  */
+      OPRND (sr) = CPU (h_gr[f_r2]);
+#undef OPRND
+    }
+    BREAK (read);
+
+    CASE (read, READ_FMT_38_MVFACHI) : /* e.g. mvfachi $dr */
+    {
+#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_38_mvfachi.f
+  EXTRACT_FMT_38_MVFACHI_VARS /* f-op1 f-r1 f-op2 f-r2 */
+
+  EXTRACT_FMT_38_MVFACHI_CODE
+
+      /* Fetch the input operands for the semantic handler.  */
+      OPRND (accum) = CPU (h_accum);
+#undef OPRND
+    }
+    BREAK (read);
+
+    CASE (read, READ_FMT_39_MVFACHI_A) : /* e.g. mvfachi $dr,$accs */
+    {
+#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_39_mvfachi_a.f
+  EXTRACT_FMT_39_MVFACHI_A_VARS /* f-op1 f-r1 f-op2 f-accs f-op3 */
+
+  EXTRACT_FMT_39_MVFACHI_A_CODE
+
+      /* Fetch the input operands for the semantic handler.  */
+      OPRND (accs) = m32rx_h_accums_get (current_cpu, f_accs);
+#undef OPRND
+    }
+    BREAK (read);
+
+    CASE (read, READ_FMT_40_MVFC) : /* e.g. mvfc $dr,$scr */
+    {
+#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_40_mvfc.f
+  EXTRACT_FMT_40_MVFC_VARS /* f-op1 f-r1 f-op2 f-r2 */
+
+  EXTRACT_FMT_40_MVFC_CODE
+
+      /* Fetch the input operands for the semantic handler.  */
+      OPRND (scr) = m32rx_h_cr_get (current_cpu, f_r2);
+#undef OPRND
+    }
+    BREAK (read);
+
+    CASE (read, READ_FMT_41_MVTACHI) : /* e.g. mvtachi $src1 */
+    {
+#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_41_mvtachi.f
+  EXTRACT_FMT_41_MVTACHI_VARS /* f-op1 f-r1 f-op2 f-r2 */
+
+  EXTRACT_FMT_41_MVTACHI_CODE
+
+      /* Fetch the input operands for the semantic handler.  */
+      OPRND (accum) = CPU (h_accum);
+      OPRND (src1) = CPU (h_gr[f_r1]);
+#undef OPRND
+    }
+    BREAK (read);
+
+    CASE (read, READ_FMT_42_MVTACHI_A) : /* e.g. mvtachi $src1,$accs */
+    {
+#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_42_mvtachi_a.f
+  EXTRACT_FMT_42_MVTACHI_A_VARS /* f-op1 f-r1 f-op2 f-accs f-op3 */
+
+  EXTRACT_FMT_42_MVTACHI_A_CODE
+
+      /* Fetch the input operands for the semantic handler.  */
+      OPRND (accs) = m32rx_h_accums_get (current_cpu, f_accs);
+      OPRND (src1) = CPU (h_gr[f_r1]);
+#undef OPRND
+    }
+    BREAK (read);
+
+    CASE (read, READ_FMT_43_MVTC) : /* e.g. mvtc $sr,$dcr */
+    {
+#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_43_mvtc.f
+  EXTRACT_FMT_43_MVTC_VARS /* f-op1 f-r1 f-op2 f-r2 */
+
+  EXTRACT_FMT_43_MVTC_CODE
+
+      /* Fetch the input operands for the semantic handler.  */
+      OPRND (sr) = CPU (h_gr[f_r2]);
+#undef OPRND
+    }
+    BREAK (read);
+
+    CASE (read, READ_FMT_44_NOP) : /* e.g. nop */
+    {
+#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_44_nop.f
+  EXTRACT_FMT_44_NOP_VARS /* f-op1 f-r1 f-op2 f-r2 */
+
+  EXTRACT_FMT_44_NOP_CODE
+
+      /* Fetch the input operands for the semantic handler.  */
+#undef OPRND
+    }
+    BREAK (read);
+
+    CASE (read, READ_FMT_45_RAC) : /* e.g. rac */
+    {
+#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_45_rac.f
+  EXTRACT_FMT_45_RAC_VARS /* f-op1 f-r1 f-op2 f-r2 */
+
+  EXTRACT_FMT_45_RAC_CODE
+
+      /* Fetch the input operands for the semantic handler.  */
+      OPRND (accum) = CPU (h_accum);
+#undef OPRND
+    }
+    BREAK (read);
+
+    CASE (read, READ_FMT_46_RAC_A) : /* e.g. rac $accs */
+    {
+#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_46_rac_a.f
+  EXTRACT_FMT_46_RAC_A_VARS /* f-op1 f-r1 f-op2 f-accs f-op3 */
+
+  EXTRACT_FMT_46_RAC_A_CODE
+
+      /* Fetch the input operands for the semantic handler.  */
+      OPRND (accs) = m32rx_h_accums_get (current_cpu, f_accs);
+#undef OPRND
+    }
+    BREAK (read);
+
+    CASE (read, READ_FMT_47_SETH) : /* e.g. seth $dr,$hi16 */
+    {
+#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_47_seth.f
+  EXTRACT_FMT_47_SETH_VARS /* f-op1 f-r1 f-op2 f-r2 f-hi16 */
+
+  EXTRACT_FMT_47_SETH_CODE
+
+      /* Fetch the input operands for the semantic handler.  */
+      OPRND (hi16) = f_hi16;
+#undef OPRND
+    }
+    BREAK (read);
+
+    CASE (read, READ_FMT_48_SLLI) : /* e.g. slli $dr,#$uimm5 */
+    {
+#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_48_slli.f
+  EXTRACT_FMT_48_SLLI_VARS /* f-op1 f-r1 f-shift-op2 f-uimm5 */
+
+  EXTRACT_FMT_48_SLLI_CODE
+
+      /* Fetch the input operands for the semantic handler.  */
+      OPRND (dr) = CPU (h_gr[f_r1]);
+      OPRND (uimm5) = f_uimm5;
+#undef OPRND
+    }
+    BREAK (read);
+
+    CASE (read, READ_FMT_49_ST_D) : /* e.g. st $src1,@($slo16,$src2) */
+    {
+#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_49_st_d.f
+  EXTRACT_FMT_49_ST_D_VARS /* f-op1 f-r1 f-op2 f-r2 f-simm16 */
+
+  EXTRACT_FMT_49_ST_D_CODE
+
+      /* Fetch the input operands for the semantic handler.  */
+      OPRND (slo16) = f_simm16;
+      OPRND (src1) = CPU (h_gr[f_r1]);
+      OPRND (src2) = CPU (h_gr[f_r2]);
+#undef OPRND
+    }
+    BREAK (read);
+
+    CASE (read, READ_FMT_50_TRAP) : /* e.g. trap #$uimm4 */
+    {
+#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_50_trap.f
+  EXTRACT_FMT_50_TRAP_VARS /* f-op1 f-r1 f-op2 f-uimm4 */
+
+  EXTRACT_FMT_50_TRAP_CODE
+
+      /* Fetch the input operands for the semantic handler.  */
+      OPRND (uimm4) = f_uimm4;
+#undef OPRND
+    }
+    BREAK (read);
+
+    CASE (read, READ_FMT_51_SATB) : /* e.g. satb $dr,$src2 */
+    {
+#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_51_satb.f
+  EXTRACT_FMT_51_SATB_VARS /* f-op1 f-r1 f-op2 f-r2 f-uimm16 */
+
+  EXTRACT_FMT_51_SATB_CODE
+
+      /* Fetch the input operands for the semantic handler.  */
+#undef OPRND
+    }
+    BREAK (read);
+
+    CASE (read, READ_FMT_52_PCMPBZ) : /* e.g. pcmpbz $src2 */
+    {
+#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_52_pcmpbz.f
+  EXTRACT_FMT_52_PCMPBZ_VARS /* f-op1 f-r1 f-op2 f-r2 */
+
+  EXTRACT_FMT_52_PCMPBZ_CODE
+
+      /* Fetch the input operands for the semantic handler.  */
+#undef OPRND
+    }
+    BREAK (read);
+
+    CASE (read, READ_FMT_53_SADD) : /* e.g. sadd */
+    {
+#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_53_sadd.f
+  EXTRACT_FMT_53_SADD_VARS /* f-op1 f-r1 f-op2 f-r2 */
+
+  EXTRACT_FMT_53_SADD_CODE
+
+      /* Fetch the input operands for the semantic handler.  */
+      OPRND (h_accums) = m32rx_h_accums_get (current_cpu, 0);
+      OPRND (h_accums) = m32rx_h_accums_get (current_cpu, 1);
+#undef OPRND
+    }
+    BREAK (read);
+
+    CASE (read, READ_FMT_54_MACWU1) : /* e.g. macwu1 $src1,$src2 */
+    {
+#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_54_macwu1.f
+  EXTRACT_FMT_54_MACWU1_VARS /* f-op1 f-r1 f-op2 f-r2 */
+
+  EXTRACT_FMT_54_MACWU1_CODE
+
+      /* Fetch the input operands for the semantic handler.  */
+      OPRND (h_accums) = m32rx_h_accums_get (current_cpu, 1);
+      OPRND (src1) = CPU (h_gr[f_r1]);
+      OPRND (src2) = CPU (h_gr[f_r2]);
+#undef OPRND
+    }
+    BREAK (read);
+
+    CASE (read, READ_FMT_55_SC) : /* e.g. sc */
+    {
+#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_55_sc.f
+  EXTRACT_FMT_55_SC_VARS /* f-op1 f-r1 f-op2 f-r2 */
+
+  EXTRACT_FMT_55_SC_CODE
+
+      /* Fetch the input operands for the semantic handler.  */
+      OPRND (condbit) = CPU (h_cond);
+#undef OPRND
+    }
+    BREAK (read);
+
+    }
+  ENDSWITCH (read) /* End of read switch.  */
+}
+
+#endif /* DEFINE_SWITCH */
diff --git a/sim/m32r/semx.c b/sim/m32r/semx.c
new file mode 100644
index 00000000000..efe9fe55f33
--- /dev/null
+++ b/sim/m32r/semx.c
@@ -0,0 +1,3188 @@
+/* Simulator instruction semantics for m32rx.
+
+Copyright (C) 1996, 1997, 1998 Free Software Foundation, Inc.
+
+This file is part of the GNU Simulators.
+
+This program is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2, or (at your option)
+any later version.
+
+This program is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License along
+with this program; if not, write to the Free Software Foundation, Inc.,
+59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+
+*/
+
+#define WANT_CPU
+#define WANT_CPU_M32RX
+
+#include "sim-main.h"
+#include "cgen-mem.h"
+#include "cgen-ops.h"
+#include "cpu-sim.h"
+
+#if ! defined (SCACHE_P) || (defined (SCACHE_P) && WITH_SCACHE)
+
+#undef GET_ATTR
+#define GET_ATTR(cpu, num, attr) CGEN_INSN_ATTR (abuf->opcode, CGEN_INSN_##attr)
+
+/* Perform add: add $dr,$sr.  */
+CIA
+SEM_FN_NAME (m32rx,add) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_0_add.f
+#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_0_add.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  CIA new_pc = SEM_NEXT_PC (sem_arg);
+  CPU (h_gr[f_r1]) = ADDSI (OPRND (dr), OPRND (sr));
+  TRACE_RESULT (current_cpu, "dr", 'x', OPRND (dr));
+#if WITH_PROFILE_MODEL_P
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      m32rx_model_mark_get_h_gr (current_cpu, abuf);
+      m32rx_model_mark_set_h_gr (current_cpu, abuf);
+      m32rx_model_profile_insn (current_cpu, abuf);
+    }
+#endif
+  return new_pc;
+#undef OPRND
+#undef FLD
+}
+
+/* Perform add3: add3 $dr,$sr,#$slo16.  */
+CIA
+SEM_FN_NAME (m32rx,add3) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_1_add3.f
+#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_1_add3.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  CIA new_pc = SEM_NEXT_PC (sem_arg);
+  CPU (h_gr[f_r1]) = ADDSI (OPRND (sr), OPRND (slo16));
+  TRACE_RESULT (current_cpu, "dr", 'x', OPRND (dr));
+#if WITH_PROFILE_MODEL_P
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      m32rx_model_mark_get_h_gr (current_cpu, abuf);
+      m32rx_model_mark_set_h_gr (current_cpu, abuf);
+      m32rx_model_profile_insn (current_cpu, abuf);
+    }
+#endif
+  return new_pc;
+#undef OPRND
+#undef FLD
+}
+
+/* Perform and: and $dr,$sr.  */
+CIA
+SEM_FN_NAME (m32rx,and) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_0_add.f
+#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_0_add.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  CIA new_pc = SEM_NEXT_PC (sem_arg);
+  CPU (h_gr[f_r1]) = ANDSI (OPRND (dr), OPRND (sr));
+  TRACE_RESULT (current_cpu, "dr", 'x', OPRND (dr));
+#if WITH_PROFILE_MODEL_P
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      m32rx_model_mark_get_h_gr (current_cpu, abuf);
+      m32rx_model_mark_set_h_gr (current_cpu, abuf);
+      m32rx_model_profile_insn (current_cpu, abuf);
+    }
+#endif
+  return new_pc;
+#undef OPRND
+#undef FLD
+}
+
+/* Perform and3: and3 $dr,$sr,#$uimm16.  */
+CIA
+SEM_FN_NAME (m32rx,and3) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_2_and3.f
+#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_2_and3.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  CIA new_pc = SEM_NEXT_PC (sem_arg);
+  CPU (h_gr[f_r1]) = ANDSI (OPRND (sr), OPRND (uimm16));
+  TRACE_RESULT (current_cpu, "dr", 'x', OPRND (dr));
+#if WITH_PROFILE_MODEL_P
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      m32rx_model_mark_get_h_gr (current_cpu, abuf);
+      m32rx_model_mark_set_h_gr (current_cpu, abuf);
+      m32rx_model_profile_insn (current_cpu, abuf);
+    }
+#endif
+  return new_pc;
+#undef OPRND
+#undef FLD
+}
+
+/* Perform or: or $dr,$sr.  */
+CIA
+SEM_FN_NAME (m32rx,or) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_0_add.f
+#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_0_add.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  CIA new_pc = SEM_NEXT_PC (sem_arg);
+  CPU (h_gr[f_r1]) = ORSI (OPRND (dr), OPRND (sr));
+  TRACE_RESULT (current_cpu, "dr", 'x', OPRND (dr));
+#if WITH_PROFILE_MODEL_P
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      m32rx_model_mark_get_h_gr (current_cpu, abuf);
+      m32rx_model_mark_set_h_gr (current_cpu, abuf);
+      m32rx_model_profile_insn (current_cpu, abuf);
+    }
+#endif
+  return new_pc;
+#undef OPRND
+#undef FLD
+}
+
+/* Perform or3: or3 $dr,$sr,#$ulo16.  */
+CIA
+SEM_FN_NAME (m32rx,or3) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_3_or3.f
+#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_3_or3.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  CIA new_pc = SEM_NEXT_PC (sem_arg);
+  CPU (h_gr[f_r1]) = ORSI (OPRND (sr), OPRND (ulo16));
+  TRACE_RESULT (current_cpu, "dr", 'x', OPRND (dr));
+#if WITH_PROFILE_MODEL_P
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      m32rx_model_mark_get_h_gr (current_cpu, abuf);
+      m32rx_model_mark_set_h_gr (current_cpu, abuf);
+      m32rx_model_profile_insn (current_cpu, abuf);
+    }
+#endif
+  return new_pc;
+#undef OPRND
+#undef FLD
+}
+
+/* Perform xor: xor $dr,$sr.  */
+CIA
+SEM_FN_NAME (m32rx,xor) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_0_add.f
+#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_0_add.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  CIA new_pc = SEM_NEXT_PC (sem_arg);
+  CPU (h_gr[f_r1]) = XORSI (OPRND (dr), OPRND (sr));
+  TRACE_RESULT (current_cpu, "dr", 'x', OPRND (dr));
+#if WITH_PROFILE_MODEL_P
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      m32rx_model_mark_get_h_gr (current_cpu, abuf);
+      m32rx_model_mark_set_h_gr (current_cpu, abuf);
+      m32rx_model_profile_insn (current_cpu, abuf);
+    }
+#endif
+  return new_pc;
+#undef OPRND
+#undef FLD
+}
+
+/* Perform xor3: xor3 $dr,$sr,#$uimm16.  */
+CIA
+SEM_FN_NAME (m32rx,xor3) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_2_and3.f
+#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_2_and3.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  CIA new_pc = SEM_NEXT_PC (sem_arg);
+  CPU (h_gr[f_r1]) = XORSI (OPRND (sr), OPRND (uimm16));
+  TRACE_RESULT (current_cpu, "dr", 'x', OPRND (dr));
+#if WITH_PROFILE_MODEL_P
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      m32rx_model_mark_get_h_gr (current_cpu, abuf);
+      m32rx_model_mark_set_h_gr (current_cpu, abuf);
+      m32rx_model_profile_insn (current_cpu, abuf);
+    }
+#endif
+  return new_pc;
+#undef OPRND
+#undef FLD
+}
+
+/* Perform addi: addi $dr,#$simm8.  */
+CIA
+SEM_FN_NAME (m32rx,addi) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_4_addi.f
+#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_4_addi.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  CIA new_pc = SEM_NEXT_PC (sem_arg);
+  CPU (h_gr[f_r1]) = ADDSI (OPRND (dr), OPRND (simm8));
+  TRACE_RESULT (current_cpu, "dr", 'x', OPRND (dr));
+#if WITH_PROFILE_MODEL_P
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      m32rx_model_mark_get_h_gr (current_cpu, abuf);
+      m32rx_model_mark_set_h_gr (current_cpu, abuf);
+      m32rx_model_profile_insn (current_cpu, abuf);
+    }
+#endif
+  return new_pc;
+#undef OPRND
+#undef FLD
+}
+
+/* Perform addv: addv $dr,$sr.  */
+CIA
+SEM_FN_NAME (m32rx,addv) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_0_add.f
+#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_0_add.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  CIA new_pc = SEM_NEXT_PC (sem_arg);
+do {
+  BI temp1;SI temp0;
+  temp0 = ADDSI (OPRND (dr), OPRND (sr));
+  temp1 = ADDOFSI (OPRND (dr), OPRND (sr), 0);
+  CPU (h_gr[f_r1]) = temp0;
+  TRACE_RESULT (current_cpu, "dr", 'x', OPRND (dr));
+  CPU (h_cond) = temp1;
+  TRACE_RESULT (current_cpu, "condbit", 'x', OPRND (condbit));
+} while (0);
+#if WITH_PROFILE_MODEL_P
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      m32rx_model_mark_get_h_gr (current_cpu, abuf);
+      m32rx_model_mark_set_h_gr (current_cpu, abuf);
+      m32rx_model_profile_insn (current_cpu, abuf);
+    }
+#endif
+  return new_pc;
+#undef OPRND
+#undef FLD
+}
+
+/* Perform addv3: addv3 $dr,$sr,#$simm16.  */
+CIA
+SEM_FN_NAME (m32rx,addv3) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_5_addv3.f
+#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_5_addv3.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  CIA new_pc = SEM_NEXT_PC (sem_arg);
+do {
+  BI temp1;SI temp0;
+  temp0 = ADDSI (OPRND (sr), OPRND (simm16));
+  temp1 = ADDOFSI (OPRND (sr), OPRND (simm16), 0);
+  CPU (h_gr[f_r1]) = temp0;
+  TRACE_RESULT (current_cpu, "dr", 'x', OPRND (dr));
+  CPU (h_cond) = temp1;
+  TRACE_RESULT (current_cpu, "condbit", 'x', OPRND (condbit));
+} while (0);
+#if WITH_PROFILE_MODEL_P
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      m32rx_model_mark_get_h_gr (current_cpu, abuf);
+      m32rx_model_mark_set_h_gr (current_cpu, abuf);
+      m32rx_model_profile_insn (current_cpu, abuf);
+    }
+#endif
+  return new_pc;
+#undef OPRND
+#undef FLD
+}
+
+/* Perform addx: addx $dr,$sr.  */
+CIA
+SEM_FN_NAME (m32rx,addx) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_6_addx.f
+#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_6_addx.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  CIA new_pc = SEM_NEXT_PC (sem_arg);
+do {
+  BI temp1;SI temp0;
+  temp0 = ADDCSI (OPRND (dr), OPRND (sr), OPRND (condbit));
+  temp1 = ADDCFSI (OPRND (dr), OPRND (sr), OPRND (condbit));
+  CPU (h_gr[f_r1]) = temp0;
+  TRACE_RESULT (current_cpu, "dr", 'x', OPRND (dr));
+  CPU (h_cond) = temp1;
+  TRACE_RESULT (current_cpu, "condbit", 'x', OPRND (condbit));
+} while (0);
+#if WITH_PROFILE_MODEL_P
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      m32rx_model_mark_get_h_gr (current_cpu, abuf);
+      m32rx_model_mark_set_h_gr (current_cpu, abuf);
+      m32rx_model_profile_insn (current_cpu, abuf);
+    }
+#endif
+  return new_pc;
+#undef OPRND
+#undef FLD
+}
+
+/* Perform bc8: bc $disp8.  */
+CIA
+SEM_FN_NAME (m32rx,bc8) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_7_bc8.f
+#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_7_bc8.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  CIA new_pc = SEM_NEXT_PC (sem_arg);
+  int taken_p = 0;
+if (OPRND (condbit)) {
+  BRANCH_NEW_PC (current_cpu, new_pc, SEM_BRANCH_VIA_CACHE (sem_arg, OPRND (disp8)));
+}
+#if WITH_PROFILE_MODEL_P
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      m32rx_model_profile_cti_insn (current_cpu, abuf, taken_p);
+    }
+#endif
+  return new_pc;
+#undef OPRND
+#undef FLD
+}
+
+/* Perform bc24: bc $disp24.  */
+CIA
+SEM_FN_NAME (m32rx,bc24) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_8_bc24.f
+#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_8_bc24.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  CIA new_pc = SEM_NEXT_PC (sem_arg);
+  int taken_p = 0;
+if (OPRND (condbit)) {
+  BRANCH_NEW_PC (current_cpu, new_pc, SEM_BRANCH_VIA_CACHE (sem_arg, OPRND (disp24)));
+}
+#if WITH_PROFILE_MODEL_P
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      m32rx_model_profile_cti_insn (current_cpu, abuf, taken_p);
+    }
+#endif
+  return new_pc;
+#undef OPRND
+#undef FLD
+}
+
+/* Perform beq: beq $src1,$src2,$disp16.  */
+CIA
+SEM_FN_NAME (m32rx,beq) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_9_beq.f
+#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_9_beq.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  CIA new_pc = SEM_NEXT_PC (sem_arg);
+  int taken_p = 0;
+if (EQSI (OPRND (src1), OPRND (src2))) {
+  BRANCH_NEW_PC (current_cpu, new_pc, SEM_BRANCH_VIA_CACHE (sem_arg, OPRND (disp16)));
+}
+#if WITH_PROFILE_MODEL_P
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      m32rx_model_mark_get_h_gr (current_cpu, abuf);
+      m32rx_model_profile_cti_insn (current_cpu, abuf, taken_p);
+    }
+#endif
+  return new_pc;
+#undef OPRND
+#undef FLD
+}
+
+/* Perform beqz: beqz $src2,$disp16.  */
+CIA
+SEM_FN_NAME (m32rx,beqz) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_10_beqz.f
+#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_10_beqz.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  CIA new_pc = SEM_NEXT_PC (sem_arg);
+  int taken_p = 0;
+if (EQSI (OPRND (src2), 0)) {
+  BRANCH_NEW_PC (current_cpu, new_pc, SEM_BRANCH_VIA_CACHE (sem_arg, OPRND (disp16)));
+}
+#if WITH_PROFILE_MODEL_P
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      m32rx_model_mark_get_h_gr (current_cpu, abuf);
+      m32rx_model_profile_cti_insn (current_cpu, abuf, taken_p);
+    }
+#endif
+  return new_pc;
+#undef OPRND
+#undef FLD
+}
+
+/* Perform bgez: bgez $src2,$disp16.  */
+CIA
+SEM_FN_NAME (m32rx,bgez) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_10_beqz.f
+#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_10_beqz.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  CIA new_pc = SEM_NEXT_PC (sem_arg);
+  int taken_p = 0;
+if (GESI (OPRND (src2), 0)) {
+  BRANCH_NEW_PC (current_cpu, new_pc, SEM_BRANCH_VIA_CACHE (sem_arg, OPRND (disp16)));
+}
+#if WITH_PROFILE_MODEL_P
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      m32rx_model_mark_get_h_gr (current_cpu, abuf);
+      m32rx_model_profile_cti_insn (current_cpu, abuf, taken_p);
+    }
+#endif
+  return new_pc;
+#undef OPRND
+#undef FLD
+}
+
+/* Perform bgtz: bgtz $src2,$disp16.  */
+CIA
+SEM_FN_NAME (m32rx,bgtz) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_10_beqz.f
+#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_10_beqz.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  CIA new_pc = SEM_NEXT_PC (sem_arg);
+  int taken_p = 0;
+if (GTSI (OPRND (src2), 0)) {
+  BRANCH_NEW_PC (current_cpu, new_pc, SEM_BRANCH_VIA_CACHE (sem_arg, OPRND (disp16)));
+}
+#if WITH_PROFILE_MODEL_P
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      m32rx_model_mark_get_h_gr (current_cpu, abuf);
+      m32rx_model_profile_cti_insn (current_cpu, abuf, taken_p);
+    }
+#endif
+  return new_pc;
+#undef OPRND
+#undef FLD
+}
+
+/* Perform blez: blez $src2,$disp16.  */
+CIA
+SEM_FN_NAME (m32rx,blez) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_10_beqz.f
+#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_10_beqz.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  CIA new_pc = SEM_NEXT_PC (sem_arg);
+  int taken_p = 0;
+if (LESI (OPRND (src2), 0)) {
+  BRANCH_NEW_PC (current_cpu, new_pc, SEM_BRANCH_VIA_CACHE (sem_arg, OPRND (disp16)));
+}
+#if WITH_PROFILE_MODEL_P
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      m32rx_model_mark_get_h_gr (current_cpu, abuf);
+      m32rx_model_profile_cti_insn (current_cpu, abuf, taken_p);
+    }
+#endif
+  return new_pc;
+#undef OPRND
+#undef FLD
+}
+
+/* Perform bltz: bltz $src2,$disp16.  */
+CIA
+SEM_FN_NAME (m32rx,bltz) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_10_beqz.f
+#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_10_beqz.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  CIA new_pc = SEM_NEXT_PC (sem_arg);
+  int taken_p = 0;
+if (LTSI (OPRND (src2), 0)) {
+  BRANCH_NEW_PC (current_cpu, new_pc, SEM_BRANCH_VIA_CACHE (sem_arg, OPRND (disp16)));
+}
+#if WITH_PROFILE_MODEL_P
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      m32rx_model_mark_get_h_gr (current_cpu, abuf);
+      m32rx_model_profile_cti_insn (current_cpu, abuf, taken_p);
+    }
+#endif
+  return new_pc;
+#undef OPRND
+#undef FLD
+}
+
+/* Perform bnez: bnez $src2,$disp16.  */
+CIA
+SEM_FN_NAME (m32rx,bnez) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_10_beqz.f
+#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_10_beqz.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  CIA new_pc = SEM_NEXT_PC (sem_arg);
+  int taken_p = 0;
+if (NESI (OPRND (src2), 0)) {
+  BRANCH_NEW_PC (current_cpu, new_pc, SEM_BRANCH_VIA_CACHE (sem_arg, OPRND (disp16)));
+}
+#if WITH_PROFILE_MODEL_P
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      m32rx_model_mark_get_h_gr (current_cpu, abuf);
+      m32rx_model_profile_cti_insn (current_cpu, abuf, taken_p);
+    }
+#endif
+  return new_pc;
+#undef OPRND
+#undef FLD
+}
+
+/* Perform bl8: bl $disp8.  */
+CIA
+SEM_FN_NAME (m32rx,bl8) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_11_bl8.f
+#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_11_bl8.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  CIA new_pc = SEM_NEXT_PC (sem_arg);
+  int taken_p = 0;
+do {
+  CPU (h_gr[14]) = ADDSI (ANDSI (OPRND (pc), -4), 4);
+  TRACE_RESULT (current_cpu, "h-gr", 'x', OPRND (h_gr));
+  BRANCH_NEW_PC (current_cpu, new_pc, SEM_BRANCH_VIA_CACHE (sem_arg, OPRND (disp8)));
+} while (0);
+#if WITH_PROFILE_MODEL_P
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      m32rx_model_profile_cti_insn (current_cpu, abuf, taken_p);
+    }
+#endif
+  return new_pc;
+#undef OPRND
+#undef FLD
+}
+
+/* Perform bl24: bl $disp24.  */
+CIA
+SEM_FN_NAME (m32rx,bl24) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_12_bl24.f
+#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_12_bl24.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  CIA new_pc = SEM_NEXT_PC (sem_arg);
+  int taken_p = 0;
+do {
+  CPU (h_gr[14]) = ADDSI (OPRND (pc), 4);
+  TRACE_RESULT (current_cpu, "h-gr", 'x', OPRND (h_gr));
+  BRANCH_NEW_PC (current_cpu, new_pc, SEM_BRANCH_VIA_CACHE (sem_arg, OPRND (disp24)));
+} while (0);
+#if WITH_PROFILE_MODEL_P
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      m32rx_model_profile_cti_insn (current_cpu, abuf, taken_p);
+    }
+#endif
+  return new_pc;
+#undef OPRND
+#undef FLD
+}
+
+/* Perform bcl8: bcl $disp8.  */
+CIA
+SEM_FN_NAME (m32rx,bcl8) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_13_bcl8.f
+#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_13_bcl8.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  CIA new_pc = SEM_NEXT_PC (sem_arg);
+  int taken_p = 0;
+if (OPRND (condbit)) {
+do {
+  CPU (h_gr[14]) = ADDSI (ANDSI (OPRND (pc), -4), 4);
+  TRACE_RESULT (current_cpu, "h-gr", 'x', OPRND (h_gr));
+  BRANCH_NEW_PC (current_cpu, new_pc, SEM_BRANCH_VIA_CACHE (sem_arg, OPRND (disp8)));
+} while (0);
+}
+#if WITH_PROFILE_MODEL_P
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      m32rx_model_mark_set_h_gr (current_cpu, abuf);
+      m32rx_model_profile_cti_insn (current_cpu, abuf, taken_p);
+    }
+#endif
+  return new_pc;
+#undef OPRND
+#undef FLD
+}
+
+/* Perform bcl24: bcl $disp24.  */
+CIA
+SEM_FN_NAME (m32rx,bcl24) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_14_bcl24.f
+#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_14_bcl24.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  CIA new_pc = SEM_NEXT_PC (sem_arg);
+  int taken_p = 0;
+if (OPRND (condbit)) {
+do {
+  CPU (h_gr[14]) = ADDSI (ANDSI (OPRND (pc), -4), 4);
+  TRACE_RESULT (current_cpu, "h-gr", 'x', OPRND (h_gr));
+  BRANCH_NEW_PC (current_cpu, new_pc, SEM_BRANCH_VIA_CACHE (sem_arg, OPRND (disp24)));
+} while (0);
+}
+#if WITH_PROFILE_MODEL_P
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      m32rx_model_mark_set_h_gr (current_cpu, abuf);
+      m32rx_model_profile_cti_insn (current_cpu, abuf, taken_p);
+    }
+#endif
+  return new_pc;
+#undef OPRND
+#undef FLD
+}
+
+/* Perform bnc8: bnc $disp8.  */
+CIA
+SEM_FN_NAME (m32rx,bnc8) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_7_bc8.f
+#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_7_bc8.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  CIA new_pc = SEM_NEXT_PC (sem_arg);
+  int taken_p = 0;
+if (NOTBI (OPRND (condbit))) {
+  BRANCH_NEW_PC (current_cpu, new_pc, SEM_BRANCH_VIA_CACHE (sem_arg, OPRND (disp8)));
+}
+#if WITH_PROFILE_MODEL_P
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      m32rx_model_profile_cti_insn (current_cpu, abuf, taken_p);
+    }
+#endif
+  return new_pc;
+#undef OPRND
+#undef FLD
+}
+
+/* Perform bnc24: bnc $disp24.  */
+CIA
+SEM_FN_NAME (m32rx,bnc24) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_8_bc24.f
+#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_8_bc24.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  CIA new_pc = SEM_NEXT_PC (sem_arg);
+  int taken_p = 0;
+if (NOTBI (OPRND (condbit))) {
+  BRANCH_NEW_PC (current_cpu, new_pc, SEM_BRANCH_VIA_CACHE (sem_arg, OPRND (disp24)));
+}
+#if WITH_PROFILE_MODEL_P
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      m32rx_model_profile_cti_insn (current_cpu, abuf, taken_p);
+    }
+#endif
+  return new_pc;
+#undef OPRND
+#undef FLD
+}
+
+/* Perform bne: bne $src1,$src2,$disp16.  */
+CIA
+SEM_FN_NAME (m32rx,bne) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_9_beq.f
+#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_9_beq.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  CIA new_pc = SEM_NEXT_PC (sem_arg);
+  int taken_p = 0;
+if (NESI (OPRND (src1), OPRND (src2))) {
+  BRANCH_NEW_PC (current_cpu, new_pc, SEM_BRANCH_VIA_CACHE (sem_arg, OPRND (disp16)));
+}
+#if WITH_PROFILE_MODEL_P
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      m32rx_model_mark_get_h_gr (current_cpu, abuf);
+      m32rx_model_profile_cti_insn (current_cpu, abuf, taken_p);
+    }
+#endif
+  return new_pc;
+#undef OPRND
+#undef FLD
+}
+
+/* Perform bra8: bra $disp8.  */
+CIA
+SEM_FN_NAME (m32rx,bra8) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_15_bra8.f
+#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_15_bra8.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  CIA new_pc = SEM_NEXT_PC (sem_arg);
+  int taken_p = 0;
+  BRANCH_NEW_PC (current_cpu, new_pc, SEM_BRANCH_VIA_CACHE (sem_arg, OPRND (disp8)));
+#if WITH_PROFILE_MODEL_P
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      m32rx_model_profile_cti_insn (current_cpu, abuf, taken_p);
+    }
+#endif
+  return new_pc;
+#undef OPRND
+#undef FLD
+}
+
+/* Perform bra24: bra $disp24.  */
+CIA
+SEM_FN_NAME (m32rx,bra24) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_16_bra24.f
+#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_16_bra24.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  CIA new_pc = SEM_NEXT_PC (sem_arg);
+  int taken_p = 0;
+  BRANCH_NEW_PC (current_cpu, new_pc, SEM_BRANCH_VIA_CACHE (sem_arg, OPRND (disp24)));
+#if WITH_PROFILE_MODEL_P
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      m32rx_model_profile_cti_insn (current_cpu, abuf, taken_p);
+    }
+#endif
+  return new_pc;
+#undef OPRND
+#undef FLD
+}
+
+/* Perform bncl8: bncl $disp8.  */
+CIA
+SEM_FN_NAME (m32rx,bncl8) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_13_bcl8.f
+#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_13_bcl8.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  CIA new_pc = SEM_NEXT_PC (sem_arg);
+  int taken_p = 0;
+if (NOTBI (OPRND (condbit))) {
+do {
+  CPU (h_gr[14]) = ADDSI (ANDSI (OPRND (pc), -4), 4);
+  TRACE_RESULT (current_cpu, "h-gr", 'x', OPRND (h_gr));
+  BRANCH_NEW_PC (current_cpu, new_pc, SEM_BRANCH_VIA_CACHE (sem_arg, OPRND (disp8)));
+} while (0);
+}
+#if WITH_PROFILE_MODEL_P
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      m32rx_model_mark_set_h_gr (current_cpu, abuf);
+      m32rx_model_profile_cti_insn (current_cpu, abuf, taken_p);
+    }
+#endif
+  return new_pc;
+#undef OPRND
+#undef FLD
+}
+
+/* Perform bncl24: bncl $disp24.  */
+CIA
+SEM_FN_NAME (m32rx,bncl24) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_14_bcl24.f
+#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_14_bcl24.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  CIA new_pc = SEM_NEXT_PC (sem_arg);
+  int taken_p = 0;
+if (NOTBI (OPRND (condbit))) {
+do {
+  CPU (h_gr[14]) = ADDSI (ANDSI (OPRND (pc), -4), 4);
+  TRACE_RESULT (current_cpu, "h-gr", 'x', OPRND (h_gr));
+  BRANCH_NEW_PC (current_cpu, new_pc, SEM_BRANCH_VIA_CACHE (sem_arg, OPRND (disp24)));
+} while (0);
+}
+#if WITH_PROFILE_MODEL_P
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      m32rx_model_mark_set_h_gr (current_cpu, abuf);
+      m32rx_model_profile_cti_insn (current_cpu, abuf, taken_p);
+    }
+#endif
+  return new_pc;
+#undef OPRND
+#undef FLD
+}
+
+/* Perform cmp: cmp $src1,$src2.  */
+CIA
+SEM_FN_NAME (m32rx,cmp) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_17_cmp.f
+#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_17_cmp.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  CIA new_pc = SEM_NEXT_PC (sem_arg);
+  CPU (h_cond) = LTSI (OPRND (src1), OPRND (src2));
+  TRACE_RESULT (current_cpu, "condbit", 'x', OPRND (condbit));
+#if WITH_PROFILE_MODEL_P
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      m32rx_model_mark_get_h_gr (current_cpu, abuf);
+      m32rx_model_profile_insn (current_cpu, abuf);
+    }
+#endif
+  return new_pc;
+#undef OPRND
+#undef FLD
+}
+
+/* Perform cmpi: cmpi $src2,#$simm16.  */
+CIA
+SEM_FN_NAME (m32rx,cmpi) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_18_cmpi.f
+#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_18_cmpi.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  CIA new_pc = SEM_NEXT_PC (sem_arg);
+  CPU (h_cond) = LTSI (OPRND (src2), OPRND (simm16));
+  TRACE_RESULT (current_cpu, "condbit", 'x', OPRND (condbit));
+#if WITH_PROFILE_MODEL_P
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      m32rx_model_mark_get_h_gr (current_cpu, abuf);
+      m32rx_model_profile_insn (current_cpu, abuf);
+    }
+#endif
+  return new_pc;
+#undef OPRND
+#undef FLD
+}
+
+/* Perform cmpu: cmpu $src1,$src2.  */
+CIA
+SEM_FN_NAME (m32rx,cmpu) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_17_cmp.f
+#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_17_cmp.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  CIA new_pc = SEM_NEXT_PC (sem_arg);
+  CPU (h_cond) = LTUSI (OPRND (src1), OPRND (src2));
+  TRACE_RESULT (current_cpu, "condbit", 'x', OPRND (condbit));
+#if WITH_PROFILE_MODEL_P
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      m32rx_model_mark_get_h_gr (current_cpu, abuf);
+      m32rx_model_profile_insn (current_cpu, abuf);
+    }
+#endif
+  return new_pc;
+#undef OPRND
+#undef FLD
+}
+
+/* Perform cmpui: cmpui $src2,#$uimm16.  */
+CIA
+SEM_FN_NAME (m32rx,cmpui) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_19_cmpui.f
+#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_19_cmpui.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  CIA new_pc = SEM_NEXT_PC (sem_arg);
+  CPU (h_cond) = LTUSI (OPRND (src2), OPRND (uimm16));
+  TRACE_RESULT (current_cpu, "condbit", 'x', OPRND (condbit));
+#if WITH_PROFILE_MODEL_P
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      m32rx_model_mark_get_h_gr (current_cpu, abuf);
+      m32rx_model_profile_insn (current_cpu, abuf);
+    }
+#endif
+  return new_pc;
+#undef OPRND
+#undef FLD
+}
+
+/* Perform cmpeq: cmpeq $src1,$src2.  */
+CIA
+SEM_FN_NAME (m32rx,cmpeq) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_17_cmp.f
+#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_17_cmp.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  CIA new_pc = SEM_NEXT_PC (sem_arg);
+  CPU (h_cond) = EQSI (OPRND (src1), OPRND (src2));
+  TRACE_RESULT (current_cpu, "condbit", 'x', OPRND (condbit));
+#if WITH_PROFILE_MODEL_P
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      m32rx_model_mark_get_h_gr (current_cpu, abuf);
+      m32rx_model_profile_insn (current_cpu, abuf);
+    }
+#endif
+  return new_pc;
+#undef OPRND
+#undef FLD
+}
+
+/* Perform cmpz: cmpz $src2.  */
+CIA
+SEM_FN_NAME (m32rx,cmpz) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_20_cmpz.f
+#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_20_cmpz.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  CIA new_pc = SEM_NEXT_PC (sem_arg);
+  CPU (h_cond) = EQSI (OPRND (src2), 0);
+  TRACE_RESULT (current_cpu, "condbit", 'x', OPRND (condbit));
+#if WITH_PROFILE_MODEL_P
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      m32rx_model_mark_get_h_gr (current_cpu, abuf);
+      m32rx_model_profile_insn (current_cpu, abuf);
+    }
+#endif
+  return new_pc;
+#undef OPRND
+#undef FLD
+}
+
+/* Perform div: div $dr,$sr.  */
+CIA
+SEM_FN_NAME (m32rx,div) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_21_div.f
+#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_21_div.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  CIA new_pc = SEM_NEXT_PC (sem_arg);
+if (NESI (OPRND (sr), 0)) {
+  CPU (h_gr[f_r1]) = DIVSI (OPRND (dr), OPRND (sr));
+  TRACE_RESULT (current_cpu, "dr", 'x', OPRND (dr));
+}
+#if WITH_PROFILE_MODEL_P
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      m32rx_model_mark_get_h_gr (current_cpu, abuf);
+      m32rx_model_mark_set_h_gr (current_cpu, abuf);
+      m32rx_model_profile_insn (current_cpu, abuf);
+    }
+#endif
+  return new_pc;
+#undef OPRND
+#undef FLD
+}
+
+/* Perform divu: divu $dr,$sr.  */
+CIA
+SEM_FN_NAME (m32rx,divu) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_21_div.f
+#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_21_div.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  CIA new_pc = SEM_NEXT_PC (sem_arg);
+if (NESI (OPRND (sr), 0)) {
+  CPU (h_gr[f_r1]) = UDIVSI (OPRND (dr), OPRND (sr));
+  TRACE_RESULT (current_cpu, "dr", 'x', OPRND (dr));
+}
+#if WITH_PROFILE_MODEL_P
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      m32rx_model_mark_get_h_gr (current_cpu, abuf);
+      m32rx_model_mark_set_h_gr (current_cpu, abuf);
+      m32rx_model_profile_insn (current_cpu, abuf);
+    }
+#endif
+  return new_pc;
+#undef OPRND
+#undef FLD
+}
+
+/* Perform rem: rem $dr,$sr.  */
+CIA
+SEM_FN_NAME (m32rx,rem) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_21_div.f
+#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_21_div.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  CIA new_pc = SEM_NEXT_PC (sem_arg);
+if (NESI (OPRND (sr), 0)) {
+  CPU (h_gr[f_r1]) = MODSI (OPRND (dr), OPRND (sr));
+  TRACE_RESULT (current_cpu, "dr", 'x', OPRND (dr));
+}
+#if WITH_PROFILE_MODEL_P
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      m32rx_model_mark_get_h_gr (current_cpu, abuf);
+      m32rx_model_mark_set_h_gr (current_cpu, abuf);
+      m32rx_model_profile_insn (current_cpu, abuf);
+    }
+#endif
+  return new_pc;
+#undef OPRND
+#undef FLD
+}
+
+/* Perform remu: remu $dr,$sr.  */
+CIA
+SEM_FN_NAME (m32rx,remu) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_21_div.f
+#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_21_div.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  CIA new_pc = SEM_NEXT_PC (sem_arg);
+if (NESI (OPRND (sr), 0)) {
+  CPU (h_gr[f_r1]) = UMODSI (OPRND (dr), OPRND (sr));
+  TRACE_RESULT (current_cpu, "dr", 'x', OPRND (dr));
+}
+#if WITH_PROFILE_MODEL_P
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      m32rx_model_mark_get_h_gr (current_cpu, abuf);
+      m32rx_model_mark_set_h_gr (current_cpu, abuf);
+      m32rx_model_profile_insn (current_cpu, abuf);
+    }
+#endif
+  return new_pc;
+#undef OPRND
+#undef FLD
+}
+
+/* Perform jc: jc $sr.  */
+CIA
+SEM_FN_NAME (m32rx,jc) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_22_jc.f
+#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_22_jc.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  CIA new_pc = SEM_NEXT_PC (sem_arg);
+  int taken_p = 0;
+if (OPRND (condbit)) {
+  BRANCH_NEW_PC (current_cpu, new_pc, SEM_BRANCH_VIA_ADDR (sem_arg, ANDSI (OPRND (sr), -4)));
+}
+#if WITH_PROFILE_MODEL_P
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      m32rx_model_mark_get_h_gr (current_cpu, abuf);
+      m32rx_model_profile_cti_insn (current_cpu, abuf, taken_p);
+    }
+#endif
+  return new_pc;
+#undef OPRND
+#undef FLD
+}
+
+/* Perform jnc: jnc $sr.  */
+CIA
+SEM_FN_NAME (m32rx,jnc) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_22_jc.f
+#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_22_jc.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  CIA new_pc = SEM_NEXT_PC (sem_arg);
+  int taken_p = 0;
+if (NOTBI (OPRND (condbit))) {
+  BRANCH_NEW_PC (current_cpu, new_pc, SEM_BRANCH_VIA_ADDR (sem_arg, ANDSI (OPRND (sr), -4)));
+}
+#if WITH_PROFILE_MODEL_P
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      m32rx_model_mark_get_h_gr (current_cpu, abuf);
+      m32rx_model_profile_cti_insn (current_cpu, abuf, taken_p);
+    }
+#endif
+  return new_pc;
+#undef OPRND
+#undef FLD
+}
+
+/* Perform jl: jl $sr.  */
+CIA
+SEM_FN_NAME (m32rx,jl) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_23_jl.f
+#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_23_jl.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  CIA new_pc = SEM_NEXT_PC (sem_arg);
+  int taken_p = 0;
+do {
+  USI temp1;SI temp0;
+  temp0 = ADDSI (ANDSI (OPRND (pc), -4), 4);
+  temp1 = OPRND (sr);
+  CPU (h_gr[14]) = temp0;
+  TRACE_RESULT (current_cpu, "h-gr", 'x', OPRND (h_gr));
+  BRANCH_NEW_PC (current_cpu, new_pc, SEM_BRANCH_VIA_ADDR (sem_arg, temp1));
+} while (0);
+#if WITH_PROFILE_MODEL_P
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      m32rx_model_mark_get_h_gr (current_cpu, abuf);
+      m32rx_model_profile_cti_insn (current_cpu, abuf, taken_p);
+    }
+#endif
+  return new_pc;
+#undef OPRND
+#undef FLD
+}
+
+/* Perform jmp: jmp $sr.  */
+CIA
+SEM_FN_NAME (m32rx,jmp) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_24_jmp.f
+#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_24_jmp.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  CIA new_pc = SEM_NEXT_PC (sem_arg);
+  int taken_p = 0;
+  BRANCH_NEW_PC (current_cpu, new_pc, SEM_BRANCH_VIA_ADDR (sem_arg, OPRND (sr)));
+#if WITH_PROFILE_MODEL_P
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      m32rx_model_mark_get_h_gr (current_cpu, abuf);
+      m32rx_model_profile_cti_insn (current_cpu, abuf, taken_p);
+    }
+#endif
+  return new_pc;
+#undef OPRND
+#undef FLD
+}
+
+/* Perform ld: ld $dr,@$sr.  */
+CIA
+SEM_FN_NAME (m32rx,ld) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_25_ld.f
+#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_25_ld.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  CIA new_pc = SEM_NEXT_PC (sem_arg);
+  CPU (h_gr[f_r1]) = OPRND (h_memory);
+  TRACE_RESULT (current_cpu, "dr", 'x', OPRND (dr));
+#if WITH_PROFILE_MODEL_P
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      m32rx_model_mark_get_h_gr (current_cpu, abuf);
+      m32rx_model_mark_set_h_gr (current_cpu, abuf);
+      m32rx_model_profile_insn (current_cpu, abuf);
+    }
+#endif
+  return new_pc;
+#undef OPRND
+#undef FLD
+}
+
+/* Perform ld-d: ld $dr,@($slo16,$sr).  */
+CIA
+SEM_FN_NAME (m32rx,ld_d) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_26_ld_d.f
+#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_26_ld_d.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  CIA new_pc = SEM_NEXT_PC (sem_arg);
+  CPU (h_gr[f_r1]) = OPRND (h_memory);
+  TRACE_RESULT (current_cpu, "dr", 'x', OPRND (dr));
+#if WITH_PROFILE_MODEL_P
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      m32rx_model_mark_get_h_gr (current_cpu, abuf);
+      m32rx_model_mark_set_h_gr (current_cpu, abuf);
+      m32rx_model_profile_insn (current_cpu, abuf);
+    }
+#endif
+  return new_pc;
+#undef OPRND
+#undef FLD
+}
+
+/* Perform ldb: ldb $dr,@$sr.  */
+CIA
+SEM_FN_NAME (m32rx,ldb) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_27_ldb.f
+#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_27_ldb.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  CIA new_pc = SEM_NEXT_PC (sem_arg);
+  CPU (h_gr[f_r1]) = EXTQISI (OPRND (h_memory));
+  TRACE_RESULT (current_cpu, "dr", 'x', OPRND (dr));
+#if WITH_PROFILE_MODEL_P
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      m32rx_model_mark_get_h_gr (current_cpu, abuf);
+      m32rx_model_mark_set_h_gr (current_cpu, abuf);
+      m32rx_model_profile_insn (current_cpu, abuf);
+    }
+#endif
+  return new_pc;
+#undef OPRND
+#undef FLD
+}
+
+/* Perform ldb-d: ldb $dr,@($slo16,$sr).  */
+CIA
+SEM_FN_NAME (m32rx,ldb_d) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_28_ldb_d.f
+#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_28_ldb_d.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  CIA new_pc = SEM_NEXT_PC (sem_arg);
+  CPU (h_gr[f_r1]) = EXTQISI (OPRND (h_memory));
+  TRACE_RESULT (current_cpu, "dr", 'x', OPRND (dr));
+#if WITH_PROFILE_MODEL_P
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      m32rx_model_mark_get_h_gr (current_cpu, abuf);
+      m32rx_model_mark_set_h_gr (current_cpu, abuf);
+      m32rx_model_profile_insn (current_cpu, abuf);
+    }
+#endif
+  return new_pc;
+#undef OPRND
+#undef FLD
+}
+
+/* Perform ldh: ldh $dr,@$sr.  */
+CIA
+SEM_FN_NAME (m32rx,ldh) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_29_ldh.f
+#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_29_ldh.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  CIA new_pc = SEM_NEXT_PC (sem_arg);
+  CPU (h_gr[f_r1]) = EXTHISI (OPRND (h_memory));
+  TRACE_RESULT (current_cpu, "dr", 'x', OPRND (dr));
+#if WITH_PROFILE_MODEL_P
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      m32rx_model_mark_get_h_gr (current_cpu, abuf);
+      m32rx_model_mark_set_h_gr (current_cpu, abuf);
+      m32rx_model_profile_insn (current_cpu, abuf);
+    }
+#endif
+  return new_pc;
+#undef OPRND
+#undef FLD
+}
+
+/* Perform ldh-d: ldh $dr,@($slo16,$sr).  */
+CIA
+SEM_FN_NAME (m32rx,ldh_d) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_30_ldh_d.f
+#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_30_ldh_d.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  CIA new_pc = SEM_NEXT_PC (sem_arg);
+  CPU (h_gr[f_r1]) = EXTHISI (OPRND (h_memory));
+  TRACE_RESULT (current_cpu, "dr", 'x', OPRND (dr));
+#if WITH_PROFILE_MODEL_P
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      m32rx_model_mark_get_h_gr (current_cpu, abuf);
+      m32rx_model_mark_set_h_gr (current_cpu, abuf);
+      m32rx_model_profile_insn (current_cpu, abuf);
+    }
+#endif
+  return new_pc;
+#undef OPRND
+#undef FLD
+}
+
+/* Perform ldub: ldub $dr,@$sr.  */
+CIA
+SEM_FN_NAME (m32rx,ldub) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_27_ldb.f
+#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_27_ldb.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  CIA new_pc = SEM_NEXT_PC (sem_arg);
+  CPU (h_gr[f_r1]) = ZEXTQISI (OPRND (h_memory));
+  TRACE_RESULT (current_cpu, "dr", 'x', OPRND (dr));
+#if WITH_PROFILE_MODEL_P
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      m32rx_model_mark_get_h_gr (current_cpu, abuf);
+      m32rx_model_mark_set_h_gr (current_cpu, abuf);
+      m32rx_model_profile_insn (current_cpu, abuf);
+    }
+#endif
+  return new_pc;
+#undef OPRND
+#undef FLD
+}
+
+/* Perform ldub-d: ldub $dr,@($slo16,$sr).  */
+CIA
+SEM_FN_NAME (m32rx,ldub_d) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_28_ldb_d.f
+#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_28_ldb_d.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  CIA new_pc = SEM_NEXT_PC (sem_arg);
+  CPU (h_gr[f_r1]) = ZEXTQISI (OPRND (h_memory));
+  TRACE_RESULT (current_cpu, "dr", 'x', OPRND (dr));
+#if WITH_PROFILE_MODEL_P
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      m32rx_model_mark_get_h_gr (current_cpu, abuf);
+      m32rx_model_mark_set_h_gr (current_cpu, abuf);
+      m32rx_model_profile_insn (current_cpu, abuf);
+    }
+#endif
+  return new_pc;
+#undef OPRND
+#undef FLD
+}
+
+/* Perform lduh: lduh $dr,@$sr.  */
+CIA
+SEM_FN_NAME (m32rx,lduh) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_29_ldh.f
+#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_29_ldh.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  CIA new_pc = SEM_NEXT_PC (sem_arg);
+  CPU (h_gr[f_r1]) = ZEXTHISI (OPRND (h_memory));
+  TRACE_RESULT (current_cpu, "dr", 'x', OPRND (dr));
+#if WITH_PROFILE_MODEL_P
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      m32rx_model_mark_get_h_gr (current_cpu, abuf);
+      m32rx_model_mark_set_h_gr (current_cpu, abuf);
+      m32rx_model_profile_insn (current_cpu, abuf);
+    }
+#endif
+  return new_pc;
+#undef OPRND
+#undef FLD
+}
+
+/* Perform lduh-d: lduh $dr,@($slo16,$sr).  */
+CIA
+SEM_FN_NAME (m32rx,lduh_d) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_30_ldh_d.f
+#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_30_ldh_d.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  CIA new_pc = SEM_NEXT_PC (sem_arg);
+  CPU (h_gr[f_r1]) = ZEXTHISI (OPRND (h_memory));
+  TRACE_RESULT (current_cpu, "dr", 'x', OPRND (dr));
+#if WITH_PROFILE_MODEL_P
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      m32rx_model_mark_get_h_gr (current_cpu, abuf);
+      m32rx_model_mark_set_h_gr (current_cpu, abuf);
+      m32rx_model_profile_insn (current_cpu, abuf);
+    }
+#endif
+  return new_pc;
+#undef OPRND
+#undef FLD
+}
+
+/* Perform ld-plus: ld $dr,@$sr+.  */
+CIA
+SEM_FN_NAME (m32rx,ld_plus) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_25_ld.f
+#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_25_ld.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  CIA new_pc = SEM_NEXT_PC (sem_arg);
+do {
+  SI temp1;SI temp0;
+  temp0 = OPRND (h_memory);
+  temp1 = ADDSI (OPRND (sr), 4);
+  CPU (h_gr[f_r1]) = temp0;
+  TRACE_RESULT (current_cpu, "dr", 'x', OPRND (dr));
+  CPU (h_gr[f_r2]) = temp1;
+  TRACE_RESULT (current_cpu, "sr", 'x', OPRND (sr));
+} while (0);
+#if WITH_PROFILE_MODEL_P
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      m32rx_model_mark_get_h_gr (current_cpu, abuf);
+      m32rx_model_mark_set_h_gr (current_cpu, abuf);
+      m32rx_model_profile_insn (current_cpu, abuf);
+    }
+#endif
+  return new_pc;
+#undef OPRND
+#undef FLD
+}
+
+/* Perform ld24: ld24 $dr,#$uimm24.  */
+CIA
+SEM_FN_NAME (m32rx,ld24) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_31_ld24.f
+#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_31_ld24.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  CIA new_pc = SEM_NEXT_PC (sem_arg);
+  CPU (h_gr[f_r1]) = OPRND (uimm24);
+  TRACE_RESULT (current_cpu, "dr", 'x', OPRND (dr));
+#if WITH_PROFILE_MODEL_P
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      m32rx_model_mark_set_h_gr (current_cpu, abuf);
+      m32rx_model_profile_insn (current_cpu, abuf);
+    }
+#endif
+  return new_pc;
+#undef OPRND
+#undef FLD
+}
+
+/* Perform ldi8: ldi $dr,#$simm8.  */
+CIA
+SEM_FN_NAME (m32rx,ldi8) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_32_ldi8.f
+#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_32_ldi8.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  CIA new_pc = SEM_NEXT_PC (sem_arg);
+  CPU (h_gr[f_r1]) = OPRND (simm8);
+  TRACE_RESULT (current_cpu, "dr", 'x', OPRND (dr));
+#if WITH_PROFILE_MODEL_P
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      m32rx_model_mark_set_h_gr (current_cpu, abuf);
+      m32rx_model_profile_insn (current_cpu, abuf);
+    }
+#endif
+  return new_pc;
+#undef OPRND
+#undef FLD
+}
+
+/* Perform ldi16: ldi $dr,$slo16.  */
+CIA
+SEM_FN_NAME (m32rx,ldi16) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_33_ldi16.f
+#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_33_ldi16.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  CIA new_pc = SEM_NEXT_PC (sem_arg);
+  CPU (h_gr[f_r1]) = OPRND (slo16);
+  TRACE_RESULT (current_cpu, "dr", 'x', OPRND (dr));
+#if WITH_PROFILE_MODEL_P
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      m32rx_model_mark_set_h_gr (current_cpu, abuf);
+      m32rx_model_profile_insn (current_cpu, abuf);
+    }
+#endif
+  return new_pc;
+#undef OPRND
+#undef FLD
+}
+
+/* Perform lock: lock $dr,@$sr.  */
+CIA
+SEM_FN_NAME (m32rx,lock) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_0_add.f
+#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_0_add.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  CIA new_pc = SEM_NEXT_PC (sem_arg);
+do_lock (current_cpu, OPRND (dr), OPRND (sr));
+#if WITH_PROFILE_MODEL_P
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      m32rx_model_mark_get_h_gr (current_cpu, abuf);
+      m32rx_model_mark_set_h_gr (current_cpu, abuf);
+      m32rx_model_profile_insn (current_cpu, abuf);
+    }
+#endif
+  return new_pc;
+#undef OPRND
+#undef FLD
+}
+
+/* Perform machi: machi $src1,$src2.  */
+CIA
+SEM_FN_NAME (m32rx,machi) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_34_machi.f
+#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_34_machi.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  CIA new_pc = SEM_NEXT_PC (sem_arg);
+  CPU (h_accum) = SRADI (SLLDI (ADDDI (OPRND (accum), MULDI (EXTSIDI (ANDSI (OPRND (src1), 0xffff0000)), EXTHIDI (TRUNCSIHI (SRASI (OPRND (src2), 16))))), 8), 8);
+  TRACE_RESULT (current_cpu, "accum", 'D', OPRND (accum));
+#if WITH_PROFILE_MODEL_P
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      m32rx_model_mark_get_h_gr (current_cpu, abuf);
+      m32rx_model_profile_insn (current_cpu, abuf);
+    }
+#endif
+  return new_pc;
+#undef OPRND
+#undef FLD
+}
+
+/* Perform machi-a: machi $src1,$src2,$acc.  */
+CIA
+SEM_FN_NAME (m32rx,machi_a) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_35_machi_a.f
+#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_35_machi_a.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  CIA new_pc = SEM_NEXT_PC (sem_arg);
+m32rx_h_accums_set (current_cpu, f_acc, SRADI (SLLDI (ADDDI (OPRND (acc), MULDI (EXTSIDI (ANDSI (OPRND (src1), 0xffff0000)), EXTHIDI (TRUNCSIHI (SRASI (OPRND (src2), 16))))), 8), 8));
+  TRACE_RESULT (current_cpu, "acc", 'D', OPRND (acc));
+#if WITH_PROFILE_MODEL_P
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      m32rx_model_mark_get_h_gr (current_cpu, abuf);
+      m32rx_model_profile_insn (current_cpu, abuf);
+    }
+#endif
+  return new_pc;
+#undef OPRND
+#undef FLD
+}
+
+/* Perform maclo: maclo $src1,$src2.  */
+CIA
+SEM_FN_NAME (m32rx,maclo) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_34_machi.f
+#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_34_machi.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  CIA new_pc = SEM_NEXT_PC (sem_arg);
+  CPU (h_accum) = SRADI (SLLDI (ADDDI (OPRND (accum), MULDI (EXTSIDI (SLLSI (OPRND (src1), 16)), EXTHIDI (TRUNCSIHI (OPRND (src2))))), 8), 8);
+  TRACE_RESULT (current_cpu, "accum", 'D', OPRND (accum));
+#if WITH_PROFILE_MODEL_P
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      m32rx_model_mark_get_h_gr (current_cpu, abuf);
+      m32rx_model_profile_insn (current_cpu, abuf);
+    }
+#endif
+  return new_pc;
+#undef OPRND
+#undef FLD
+}
+
+/* Perform maclo-a: maclo $src1,$src2,$acc.  */
+CIA
+SEM_FN_NAME (m32rx,maclo_a) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_35_machi_a.f
+#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_35_machi_a.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  CIA new_pc = SEM_NEXT_PC (sem_arg);
+m32rx_h_accums_set (current_cpu, f_acc, SRADI (SLLDI (ADDDI (OPRND (acc), MULDI (EXTSIDI (SLLSI (OPRND (src1), 16)), EXTHIDI (TRUNCSIHI (OPRND (src2))))), 8), 8));
+  TRACE_RESULT (current_cpu, "acc", 'D', OPRND (acc));
+#if WITH_PROFILE_MODEL_P
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      m32rx_model_mark_get_h_gr (current_cpu, abuf);
+      m32rx_model_profile_insn (current_cpu, abuf);
+    }
+#endif
+  return new_pc;
+#undef OPRND
+#undef FLD
+}
+
+/* Perform macwhi: macwhi $src1,$src2.  */
+CIA
+SEM_FN_NAME (m32rx,macwhi) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_34_machi.f
+#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_34_machi.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  CIA new_pc = SEM_NEXT_PC (sem_arg);
+  CPU (h_accum) = SRADI (SLLDI (ADDDI (OPRND (accum), MULDI (EXTSIDI (OPRND (src1)), EXTHIDI (TRUNCSIHI (SRASI (OPRND (src2), 16))))), 8), 8);
+  TRACE_RESULT (current_cpu, "accum", 'D', OPRND (accum));
+#if WITH_PROFILE_MODEL_P
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      m32rx_model_mark_get_h_gr (current_cpu, abuf);
+      m32rx_model_profile_insn (current_cpu, abuf);
+    }
+#endif
+  return new_pc;
+#undef OPRND
+#undef FLD
+}
+
+/* Perform macwhi-a: macwhi $src1,$src2,$acc.  */
+CIA
+SEM_FN_NAME (m32rx,macwhi_a) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_35_machi_a.f
+#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_35_machi_a.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  CIA new_pc = SEM_NEXT_PC (sem_arg);
+m32rx_h_accums_set (current_cpu, f_acc, SRADI (SLLDI (ADDDI (OPRND (acc), MULDI (EXTSIDI (OPRND (src1)), EXTHIDI (TRUNCSIHI (SRASI (OPRND (src2), 16))))), 8), 8));
+  TRACE_RESULT (current_cpu, "acc", 'D', OPRND (acc));
+#if WITH_PROFILE_MODEL_P
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      m32rx_model_mark_get_h_gr (current_cpu, abuf);
+      m32rx_model_profile_insn (current_cpu, abuf);
+    }
+#endif
+  return new_pc;
+#undef OPRND
+#undef FLD
+}
+
+/* Perform macwlo: macwlo $src1,$src2.  */
+CIA
+SEM_FN_NAME (m32rx,macwlo) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_34_machi.f
+#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_34_machi.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  CIA new_pc = SEM_NEXT_PC (sem_arg);
+  CPU (h_accum) = SRADI (SLLDI (ADDDI (OPRND (accum), MULDI (EXTSIDI (OPRND (src1)), EXTHIDI (TRUNCSIHI (OPRND (src2))))), 8), 8);
+  TRACE_RESULT (current_cpu, "accum", 'D', OPRND (accum));
+#if WITH_PROFILE_MODEL_P
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      m32rx_model_mark_get_h_gr (current_cpu, abuf);
+      m32rx_model_profile_insn (current_cpu, abuf);
+    }
+#endif
+  return new_pc;
+#undef OPRND
+#undef FLD
+}
+
+/* Perform macwlo-a: macwlo $src1,$src2,$acc.  */
+CIA
+SEM_FN_NAME (m32rx,macwlo_a) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_35_machi_a.f
+#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_35_machi_a.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  CIA new_pc = SEM_NEXT_PC (sem_arg);
+m32rx_h_accums_set (current_cpu, f_acc, SRADI (SLLDI (ADDDI (OPRND (acc), MULDI (EXTSIDI (OPRND (src1)), EXTHIDI (TRUNCSIHI (OPRND (src2))))), 8), 8));
+  TRACE_RESULT (current_cpu, "acc", 'D', OPRND (acc));
+#if WITH_PROFILE_MODEL_P
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      m32rx_model_mark_get_h_gr (current_cpu, abuf);
+      m32rx_model_profile_insn (current_cpu, abuf);
+    }
+#endif
+  return new_pc;
+#undef OPRND
+#undef FLD
+}
+
+/* Perform mul: mul $dr,$sr.  */
+CIA
+SEM_FN_NAME (m32rx,mul) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_0_add.f
+#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_0_add.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  CIA new_pc = SEM_NEXT_PC (sem_arg);
+  CPU (h_gr[f_r1]) = MULSI (OPRND (dr), OPRND (sr));
+  TRACE_RESULT (current_cpu, "dr", 'x', OPRND (dr));
+#if WITH_PROFILE_MODEL_P
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      m32rx_model_mark_get_h_gr (current_cpu, abuf);
+      m32rx_model_mark_set_h_gr (current_cpu, abuf);
+      m32rx_model_profile_insn (current_cpu, abuf);
+    }
+#endif
+  return new_pc;
+#undef OPRND
+#undef FLD
+}
+
+/* Perform mulhi: mulhi $src1,$src2.  */
+CIA
+SEM_FN_NAME (m32rx,mulhi) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_17_cmp.f
+#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_17_cmp.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  CIA new_pc = SEM_NEXT_PC (sem_arg);
+  CPU (h_accum) = SRADI (SLLDI (MULDI (EXTSIDI (ANDSI (OPRND (src1), 0xffff0000)), EXTHIDI (TRUNCSIHI (SRASI (OPRND (src2), 16)))), 16), 16);
+  TRACE_RESULT (current_cpu, "accum", 'D', OPRND (accum));
+#if WITH_PROFILE_MODEL_P
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      m32rx_model_mark_get_h_gr (current_cpu, abuf);
+      m32rx_model_profile_insn (current_cpu, abuf);
+    }
+#endif
+  return new_pc;
+#undef OPRND
+#undef FLD
+}
+
+/* Perform mulhi-a: mulhi $src1,$src2,$acc.  */
+CIA
+SEM_FN_NAME (m32rx,mulhi_a) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_36_mulhi_a.f
+#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_36_mulhi_a.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  CIA new_pc = SEM_NEXT_PC (sem_arg);
+m32rx_h_accums_set (current_cpu, f_acc, SRADI (SLLDI (MULDI (EXTSIDI (ANDSI (OPRND (src1), 0xffff0000)), EXTHIDI (TRUNCSIHI (SRASI (OPRND (src2), 16)))), 16), 16));
+  TRACE_RESULT (current_cpu, "acc", 'D', OPRND (acc));
+#if WITH_PROFILE_MODEL_P
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      m32rx_model_mark_get_h_gr (current_cpu, abuf);
+      m32rx_model_profile_insn (current_cpu, abuf);
+    }
+#endif
+  return new_pc;
+#undef OPRND
+#undef FLD
+}
+
+/* Perform mullo: mullo $src1,$src2.  */
+CIA
+SEM_FN_NAME (m32rx,mullo) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_17_cmp.f
+#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_17_cmp.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  CIA new_pc = SEM_NEXT_PC (sem_arg);
+  CPU (h_accum) = SRADI (SLLDI (MULDI (EXTSIDI (SLLSI (OPRND (src1), 16)), EXTHIDI (TRUNCSIHI (OPRND (src2)))), 16), 16);
+  TRACE_RESULT (current_cpu, "accum", 'D', OPRND (accum));
+#if WITH_PROFILE_MODEL_P
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      m32rx_model_mark_get_h_gr (current_cpu, abuf);
+      m32rx_model_profile_insn (current_cpu, abuf);
+    }
+#endif
+  return new_pc;
+#undef OPRND
+#undef FLD
+}
+
+/* Perform mullo-a: mullo $src1,$src2,$acc.  */
+CIA
+SEM_FN_NAME (m32rx,mullo_a) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_36_mulhi_a.f
+#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_36_mulhi_a.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  CIA new_pc = SEM_NEXT_PC (sem_arg);
+m32rx_h_accums_set (current_cpu, f_acc, SRADI (SLLDI (MULDI (EXTSIDI (SLLSI (OPRND (src1), 16)), EXTHIDI (TRUNCSIHI (OPRND (src2)))), 16), 16));
+  TRACE_RESULT (current_cpu, "acc", 'D', OPRND (acc));
+#if WITH_PROFILE_MODEL_P
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      m32rx_model_mark_get_h_gr (current_cpu, abuf);
+      m32rx_model_profile_insn (current_cpu, abuf);
+    }
+#endif
+  return new_pc;
+#undef OPRND
+#undef FLD
+}
+
+/* Perform mulwhi: mulwhi $src1,$src2.  */
+CIA
+SEM_FN_NAME (m32rx,mulwhi) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_17_cmp.f
+#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_17_cmp.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  CIA new_pc = SEM_NEXT_PC (sem_arg);
+  CPU (h_accum) = SRADI (SLLDI (MULDI (EXTSIDI (OPRND (src1)), EXTHIDI (TRUNCSIHI (SRASI (OPRND (src2), 16)))), 8), 8);
+  TRACE_RESULT (current_cpu, "accum", 'D', OPRND (accum));
+#if WITH_PROFILE_MODEL_P
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      m32rx_model_mark_get_h_gr (current_cpu, abuf);
+      m32rx_model_profile_insn (current_cpu, abuf);
+    }
+#endif
+  return new_pc;
+#undef OPRND
+#undef FLD
+}
+
+/* Perform mulwhi-a: mulwhi $src1,$src2,$acc.  */
+CIA
+SEM_FN_NAME (m32rx,mulwhi_a) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_36_mulhi_a.f
+#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_36_mulhi_a.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  CIA new_pc = SEM_NEXT_PC (sem_arg);
+m32rx_h_accums_set (current_cpu, f_acc, SRADI (SLLDI (MULDI (EXTSIDI (OPRND (src1)), EXTHIDI (TRUNCSIHI (SRASI (OPRND (src2), 16)))), 8), 8));
+  TRACE_RESULT (current_cpu, "acc", 'D', OPRND (acc));
+#if WITH_PROFILE_MODEL_P
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      m32rx_model_mark_get_h_gr (current_cpu, abuf);
+      m32rx_model_profile_insn (current_cpu, abuf);
+    }
+#endif
+  return new_pc;
+#undef OPRND
+#undef FLD
+}
+
+/* Perform mulwlo: mulwlo $src1,$src2.  */
+CIA
+SEM_FN_NAME (m32rx,mulwlo) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_17_cmp.f
+#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_17_cmp.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  CIA new_pc = SEM_NEXT_PC (sem_arg);
+  CPU (h_accum) = SRADI (SLLDI (MULDI (EXTSIDI (OPRND (src1)), EXTHIDI (TRUNCSIHI (OPRND (src2)))), 8), 8);
+  TRACE_RESULT (current_cpu, "accum", 'D', OPRND (accum));
+#if WITH_PROFILE_MODEL_P
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      m32rx_model_mark_get_h_gr (current_cpu, abuf);
+      m32rx_model_profile_insn (current_cpu, abuf);
+    }
+#endif
+  return new_pc;
+#undef OPRND
+#undef FLD
+}
+
+/* Perform mulwlo-a: mulwlo $src1,$src2,$acc.  */
+CIA
+SEM_FN_NAME (m32rx,mulwlo_a) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_36_mulhi_a.f
+#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_36_mulhi_a.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  CIA new_pc = SEM_NEXT_PC (sem_arg);
+m32rx_h_accums_set (current_cpu, f_acc, SRADI (SLLDI (MULDI (EXTSIDI (OPRND (src1)), EXTHIDI (TRUNCSIHI (OPRND (src2)))), 8), 8));
+  TRACE_RESULT (current_cpu, "acc", 'D', OPRND (acc));
+#if WITH_PROFILE_MODEL_P
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      m32rx_model_mark_get_h_gr (current_cpu, abuf);
+      m32rx_model_profile_insn (current_cpu, abuf);
+    }
+#endif
+  return new_pc;
+#undef OPRND
+#undef FLD
+}
+
+/* Perform mv: mv $dr,$sr.  */
+CIA
+SEM_FN_NAME (m32rx,mv) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_37_mv.f
+#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_37_mv.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  CIA new_pc = SEM_NEXT_PC (sem_arg);
+  CPU (h_gr[f_r1]) = OPRND (sr);
+  TRACE_RESULT (current_cpu, "dr", 'x', OPRND (dr));
+#if WITH_PROFILE_MODEL_P
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      m32rx_model_mark_get_h_gr (current_cpu, abuf);
+      m32rx_model_mark_set_h_gr (current_cpu, abuf);
+      m32rx_model_profile_insn (current_cpu, abuf);
+    }
+#endif
+  return new_pc;
+#undef OPRND
+#undef FLD
+}
+
+/* Perform mvfachi: mvfachi $dr.  */
+CIA
+SEM_FN_NAME (m32rx,mvfachi) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_38_mvfachi.f
+#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_38_mvfachi.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  CIA new_pc = SEM_NEXT_PC (sem_arg);
+  CPU (h_gr[f_r1]) = TRUNCDISI (SRADI (OPRND (accum), 32));
+  TRACE_RESULT (current_cpu, "dr", 'x', OPRND (dr));
+#if WITH_PROFILE_MODEL_P
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      m32rx_model_mark_set_h_gr (current_cpu, abuf);
+      m32rx_model_profile_insn (current_cpu, abuf);
+    }
+#endif
+  return new_pc;
+#undef OPRND
+#undef FLD
+}
+
+/* Perform mvfachi-a: mvfachi $dr,$accs.  */
+CIA
+SEM_FN_NAME (m32rx,mvfachi_a) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_39_mvfachi_a.f
+#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_39_mvfachi_a.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  CIA new_pc = SEM_NEXT_PC (sem_arg);
+  CPU (h_gr[f_r1]) = TRUNCDISI (SRADI (OPRND (accs), 32));
+  TRACE_RESULT (current_cpu, "dr", 'x', OPRND (dr));
+#if WITH_PROFILE_MODEL_P
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      m32rx_model_mark_set_h_gr (current_cpu, abuf);
+      m32rx_model_profile_insn (current_cpu, abuf);
+    }
+#endif
+  return new_pc;
+#undef OPRND
+#undef FLD
+}
+
+/* Perform mvfaclo: mvfaclo $dr.  */
+CIA
+SEM_FN_NAME (m32rx,mvfaclo) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_38_mvfachi.f
+#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_38_mvfachi.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  CIA new_pc = SEM_NEXT_PC (sem_arg);
+  CPU (h_gr[f_r1]) = TRUNCDISI (OPRND (accum));
+  TRACE_RESULT (current_cpu, "dr", 'x', OPRND (dr));
+#if WITH_PROFILE_MODEL_P
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      m32rx_model_mark_set_h_gr (current_cpu, abuf);
+      m32rx_model_profile_insn (current_cpu, abuf);
+    }
+#endif
+  return new_pc;
+#undef OPRND
+#undef FLD
+}
+
+/* Perform mvfaclo-a: mvfaclo $dr,$accs.  */
+CIA
+SEM_FN_NAME (m32rx,mvfaclo_a) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_39_mvfachi_a.f
+#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_39_mvfachi_a.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  CIA new_pc = SEM_NEXT_PC (sem_arg);
+  CPU (h_gr[f_r1]) = TRUNCDISI (OPRND (accs));
+  TRACE_RESULT (current_cpu, "dr", 'x', OPRND (dr));
+#if WITH_PROFILE_MODEL_P
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      m32rx_model_mark_set_h_gr (current_cpu, abuf);
+      m32rx_model_profile_insn (current_cpu, abuf);
+    }
+#endif
+  return new_pc;
+#undef OPRND
+#undef FLD
+}
+
+/* Perform mvfacmi: mvfacmi $dr.  */
+CIA
+SEM_FN_NAME (m32rx,mvfacmi) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_38_mvfachi.f
+#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_38_mvfachi.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  CIA new_pc = SEM_NEXT_PC (sem_arg);
+  CPU (h_gr[f_r1]) = TRUNCDISI (SRADI (OPRND (accum), 16));
+  TRACE_RESULT (current_cpu, "dr", 'x', OPRND (dr));
+#if WITH_PROFILE_MODEL_P
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      m32rx_model_mark_set_h_gr (current_cpu, abuf);
+      m32rx_model_profile_insn (current_cpu, abuf);
+    }
+#endif
+  return new_pc;
+#undef OPRND
+#undef FLD
+}
+
+/* Perform mvfacmi-a: mvfacmi $dr,$accs.  */
+CIA
+SEM_FN_NAME (m32rx,mvfacmi_a) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_39_mvfachi_a.f
+#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_39_mvfachi_a.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  CIA new_pc = SEM_NEXT_PC (sem_arg);
+  CPU (h_gr[f_r1]) = TRUNCDISI (SRADI (OPRND (accs), 16));
+  TRACE_RESULT (current_cpu, "dr", 'x', OPRND (dr));
+#if WITH_PROFILE_MODEL_P
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      m32rx_model_mark_set_h_gr (current_cpu, abuf);
+      m32rx_model_profile_insn (current_cpu, abuf);
+    }
+#endif
+  return new_pc;
+#undef OPRND
+#undef FLD
+}
+
+/* Perform mvfc: mvfc $dr,$scr.  */
+CIA
+SEM_FN_NAME (m32rx,mvfc) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_40_mvfc.f
+#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_40_mvfc.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  CIA new_pc = SEM_NEXT_PC (sem_arg);
+  CPU (h_gr[f_r1]) = OPRND (scr);
+  TRACE_RESULT (current_cpu, "dr", 'x', OPRND (dr));
+#if WITH_PROFILE_MODEL_P
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      m32rx_model_mark_set_h_gr (current_cpu, abuf);
+      m32rx_model_profile_insn (current_cpu, abuf);
+    }
+#endif
+  return new_pc;
+#undef OPRND
+#undef FLD
+}
+
+/* Perform mvtachi: mvtachi $src1.  */
+CIA
+SEM_FN_NAME (m32rx,mvtachi) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_41_mvtachi.f
+#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_41_mvtachi.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  CIA new_pc = SEM_NEXT_PC (sem_arg);
+  CPU (h_accum) = ORDI (ANDDI (OPRND (accum), MAKEDI (0, 0xffffffff)), SLLDI (EXTSIDI (OPRND (src1)), 32));
+  TRACE_RESULT (current_cpu, "accum", 'D', OPRND (accum));
+#if WITH_PROFILE_MODEL_P
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      m32rx_model_mark_get_h_gr (current_cpu, abuf);
+      m32rx_model_profile_insn (current_cpu, abuf);
+    }
+#endif
+  return new_pc;
+#undef OPRND
+#undef FLD
+}
+
+/* Perform mvtachi-a: mvtachi $src1,$accs.  */
+CIA
+SEM_FN_NAME (m32rx,mvtachi_a) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_42_mvtachi_a.f
+#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_42_mvtachi_a.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  CIA new_pc = SEM_NEXT_PC (sem_arg);
+m32rx_h_accums_set (current_cpu, f_accs, ORDI (ANDDI (OPRND (accs), MAKEDI (0, 0xffffffff)), SLLDI (EXTSIDI (OPRND (src1)), 32)));
+  TRACE_RESULT (current_cpu, "accs", 'D', OPRND (accs));
+#if WITH_PROFILE_MODEL_P
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      m32rx_model_mark_get_h_gr (current_cpu, abuf);
+      m32rx_model_profile_insn (current_cpu, abuf);
+    }
+#endif
+  return new_pc;
+#undef OPRND
+#undef FLD
+}
+
+/* Perform mvtaclo: mvtaclo $src1.  */
+CIA
+SEM_FN_NAME (m32rx,mvtaclo) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_41_mvtachi.f
+#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_41_mvtachi.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  CIA new_pc = SEM_NEXT_PC (sem_arg);
+  CPU (h_accum) = ORDI (ANDDI (OPRND (accum), MAKEDI (0xffffffff, 0)), EXTSIDI (OPRND (src1)));
+  TRACE_RESULT (current_cpu, "accum", 'D', OPRND (accum));
+#if WITH_PROFILE_MODEL_P
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      m32rx_model_mark_get_h_gr (current_cpu, abuf);
+      m32rx_model_profile_insn (current_cpu, abuf);
+    }
+#endif
+  return new_pc;
+#undef OPRND
+#undef FLD
+}
+
+/* Perform mvtaclo-a: mvtaclo $src1,$accs.  */
+CIA
+SEM_FN_NAME (m32rx,mvtaclo_a) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_42_mvtachi_a.f
+#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_42_mvtachi_a.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  CIA new_pc = SEM_NEXT_PC (sem_arg);
+m32rx_h_accums_set (current_cpu, f_accs, ORDI (ANDDI (OPRND (accs), MAKEDI (0xffffffff, 0)), EXTSIDI (OPRND (src1))));
+  TRACE_RESULT (current_cpu, "accs", 'D', OPRND (accs));
+#if WITH_PROFILE_MODEL_P
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      m32rx_model_mark_get_h_gr (current_cpu, abuf);
+      m32rx_model_profile_insn (current_cpu, abuf);
+    }
+#endif
+  return new_pc;
+#undef OPRND
+#undef FLD
+}
+
+/* Perform mvtc: mvtc $sr,$dcr.  */
+CIA
+SEM_FN_NAME (m32rx,mvtc) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_43_mvtc.f
+#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_43_mvtc.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  CIA new_pc = SEM_NEXT_PC (sem_arg);
+m32rx_h_cr_set (current_cpu, f_r1, OPRND (sr));
+  TRACE_RESULT (current_cpu, "dcr", 'x', OPRND (dcr));
+#if WITH_PROFILE_MODEL_P
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      m32rx_model_mark_get_h_gr (current_cpu, abuf);
+      m32rx_model_profile_insn (current_cpu, abuf);
+    }
+#endif
+  return new_pc;
+#undef OPRND
+#undef FLD
+}
+
+/* Perform neg: neg $dr,$sr.  */
+CIA
+SEM_FN_NAME (m32rx,neg) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_37_mv.f
+#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_37_mv.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  CIA new_pc = SEM_NEXT_PC (sem_arg);
+  CPU (h_gr[f_r1]) = NEGSI (OPRND (sr));
+  TRACE_RESULT (current_cpu, "dr", 'x', OPRND (dr));
+#if WITH_PROFILE_MODEL_P
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      m32rx_model_mark_get_h_gr (current_cpu, abuf);
+      m32rx_model_mark_set_h_gr (current_cpu, abuf);
+      m32rx_model_profile_insn (current_cpu, abuf);
+    }
+#endif
+  return new_pc;
+#undef OPRND
+#undef FLD
+}
+
+/* Perform nop: nop.  */
+CIA
+SEM_FN_NAME (m32rx,nop) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_44_nop.f
+#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_44_nop.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  CIA new_pc = SEM_NEXT_PC (sem_arg);
+PROFILE_COUNT_FILLNOPS (current_cpu, abuf->addr);
+#if WITH_PROFILE_MODEL_P
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      m32rx_model_profile_insn (current_cpu, abuf);
+    }
+#endif
+  return new_pc;
+#undef OPRND
+#undef FLD
+}
+
+/* Perform not: not $dr,$sr.  */
+CIA
+SEM_FN_NAME (m32rx,not) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_37_mv.f
+#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_37_mv.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  CIA new_pc = SEM_NEXT_PC (sem_arg);
+  CPU (h_gr[f_r1]) = INVSI (OPRND (sr));
+  TRACE_RESULT (current_cpu, "dr", 'x', OPRND (dr));
+#if WITH_PROFILE_MODEL_P
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      m32rx_model_mark_get_h_gr (current_cpu, abuf);
+      m32rx_model_mark_set_h_gr (current_cpu, abuf);
+      m32rx_model_profile_insn (current_cpu, abuf);
+    }
+#endif
+  return new_pc;
+#undef OPRND
+#undef FLD
+}
+
+/* Perform rac: rac.  */
+CIA
+SEM_FN_NAME (m32rx,rac) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_45_rac.f
+#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_45_rac.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  CIA new_pc = SEM_NEXT_PC (sem_arg);
+do {
+  DI tmp_tmp1;
+  tmp_tmp1 = ANDDI (OPRND (accum), MAKEDI (16777215, 0xffffffff));
+if (ANDIFSI (GEDI (tmp_tmp1, MAKEDI (16383, 0xffff8000)), LEDI (tmp_tmp1, MAKEDI (8388607, 0xffffffff)))) {
+  tmp_tmp1 = MAKEDI (16383, 0xffff8000);
+} else {
+if (ANDIFSI (GEDI (tmp_tmp1, MAKEDI (8388608, 0)), LEDI (tmp_tmp1, MAKEDI (16760832, 0)))) {
+  tmp_tmp1 = MAKEDI (16760832, 0);
+} else {
+  tmp_tmp1 = ANDDI (ADDDI (OPRND (accum), MAKEDI (0, 16384)), MAKEDI (16777215, 0xffff8000));
+}
+}
+  tmp_tmp1 = SLLDI (tmp_tmp1, 1);
+  CPU (h_accum) = SRADI (SLLDI (tmp_tmp1, 7), 7);
+  TRACE_RESULT (current_cpu, "accum", 'D', OPRND (accum));
+} while (0);
+#if WITH_PROFILE_MODEL_P
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      m32rx_model_profile_insn (current_cpu, abuf);
+    }
+#endif
+  return new_pc;
+#undef OPRND
+#undef FLD
+}
+
+/* Perform rac-a: rac $accs.  */
+CIA
+SEM_FN_NAME (m32rx,rac_a) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_46_rac_a.f
+#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_46_rac_a.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  CIA new_pc = SEM_NEXT_PC (sem_arg);
+do {
+  DI tmp_tmp1;
+  tmp_tmp1 = ANDDI (OPRND (accs), MAKEDI (16777215, 0xffffffff));
+if (ANDIFSI (GEDI (tmp_tmp1, MAKEDI (16383, 0xffff8000)), LEDI (tmp_tmp1, MAKEDI (8388607, 0xffffffff)))) {
+  tmp_tmp1 = MAKEDI (16383, 0xffff8000);
+} else {
+if (ANDIFSI (GEDI (tmp_tmp1, MAKEDI (8388608, 0)), LEDI (tmp_tmp1, MAKEDI (16760832, 0)))) {
+  tmp_tmp1 = MAKEDI (16760832, 0);
+} else {
+  tmp_tmp1 = ANDDI (ADDDI (OPRND (accs), MAKEDI (0, 16384)), MAKEDI (16777215, 0xffff8000));
+}
+}
+  tmp_tmp1 = SLLDI (tmp_tmp1, 1);
+m32rx_h_accums_set (current_cpu, f_accs, SRADI (SLLDI (tmp_tmp1, 7), 7));
+  TRACE_RESULT (current_cpu, "accs", 'D', OPRND (accs));
+} while (0);
+#if WITH_PROFILE_MODEL_P
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      m32rx_model_profile_insn (current_cpu, abuf);
+    }
+#endif
+  return new_pc;
+#undef OPRND
+#undef FLD
+}
+
+/* Perform rach: rach.  */
+CIA
+SEM_FN_NAME (m32rx,rach) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_45_rac.f
+#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_45_rac.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  CIA new_pc = SEM_NEXT_PC (sem_arg);
+do {
+  DI tmp_tmp1;
+  tmp_tmp1 = ANDDI (OPRND (accum), MAKEDI (16777215, 0xffffffff));
+if (ANDIFSI (GEDI (tmp_tmp1, MAKEDI (16383, 0x80000000)), LEDI (tmp_tmp1, MAKEDI (8388607, 0xffffffff)))) {
+  tmp_tmp1 = MAKEDI (16383, 0x80000000);
+} else {
+if (ANDIFSI (GEDI (tmp_tmp1, MAKEDI (8388608, 0)), LEDI (tmp_tmp1, MAKEDI (16760832, 0)))) {
+  tmp_tmp1 = MAKEDI (16760832, 0);
+} else {
+  tmp_tmp1 = ANDDI (ADDDI (OPRND (accum), MAKEDI (0, 1073741824)), MAKEDI (0xffffffff, 0x80000000));
+}
+}
+  tmp_tmp1 = SLLDI (tmp_tmp1, 1);
+  CPU (h_accum) = SRADI (SLLDI (tmp_tmp1, 7), 7);
+  TRACE_RESULT (current_cpu, "accum", 'D', OPRND (accum));
+} while (0);
+#if WITH_PROFILE_MODEL_P
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      m32rx_model_profile_insn (current_cpu, abuf);
+    }
+#endif
+  return new_pc;
+#undef OPRND
+#undef FLD
+}
+
+/* Perform rach-a: rach $accs.  */
+CIA
+SEM_FN_NAME (m32rx,rach_a) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_46_rac_a.f
+#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_46_rac_a.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  CIA new_pc = SEM_NEXT_PC (sem_arg);
+do {
+  DI tmp_tmp1;
+  tmp_tmp1 = ANDDI (OPRND (accs), MAKEDI (16777215, 0xffffffff));
+if (ANDIFSI (GEDI (tmp_tmp1, MAKEDI (16383, 0x80000000)), LEDI (tmp_tmp1, MAKEDI (8388607, 0xffffffff)))) {
+  tmp_tmp1 = MAKEDI (16383, 0x80000000);
+} else {
+if (ANDIFSI (GEDI (tmp_tmp1, MAKEDI (8388608, 0)), LEDI (tmp_tmp1, MAKEDI (16760832, 0)))) {
+  tmp_tmp1 = MAKEDI (16760832, 0);
+} else {
+  tmp_tmp1 = ANDDI (ADDDI (OPRND (accs), MAKEDI (0, 1073741824)), MAKEDI (0xffffffff, 0x80000000));
+}
+}
+  tmp_tmp1 = SLLDI (tmp_tmp1, 1);
+m32rx_h_accums_set (current_cpu, f_accs, SRADI (SLLDI (tmp_tmp1, 7), 7));
+  TRACE_RESULT (current_cpu, "accs", 'D', OPRND (accs));
+} while (0);
+#if WITH_PROFILE_MODEL_P
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      m32rx_model_profile_insn (current_cpu, abuf);
+    }
+#endif
+  return new_pc;
+#undef OPRND
+#undef FLD
+}
+
+/* Perform rte: rte.  */
+CIA
+SEM_FN_NAME (m32rx,rte) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_44_nop.f
+#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_44_nop.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  CIA new_pc = SEM_NEXT_PC (sem_arg);
+  int taken_p = 0;
+do {
+  CPU (h_sm) = OPRND (h_bsm);
+  TRACE_RESULT (current_cpu, "h-sm", 'x', OPRND (h_sm));
+  CPU (h_ie) = OPRND (h_bie);
+  TRACE_RESULT (current_cpu, "h-ie", 'x', OPRND (h_ie));
+  CPU (h_cond) = OPRND (h_bcond);
+  TRACE_RESULT (current_cpu, "condbit", 'x', OPRND (condbit));
+  BRANCH_NEW_PC (current_cpu, new_pc, SEM_BRANCH_VIA_ADDR (sem_arg, OPRND (h_bpc)));
+  TRACE_RESULT (current_cpu, "pc", 'x', OPRND (pc));
+} while (0);
+#if WITH_PROFILE_MODEL_P
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      m32rx_model_profile_cti_insn (current_cpu, abuf, taken_p);
+    }
+#endif
+  return new_pc;
+#undef OPRND
+#undef FLD
+}
+
+/* Perform seth: seth $dr,$hi16.  */
+CIA
+SEM_FN_NAME (m32rx,seth) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_47_seth.f
+#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_47_seth.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  CIA new_pc = SEM_NEXT_PC (sem_arg);
+  CPU (h_gr[f_r1]) = SLLSI (OPRND (hi16), 16);
+  TRACE_RESULT (current_cpu, "dr", 'x', OPRND (dr));
+#if WITH_PROFILE_MODEL_P
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      m32rx_model_mark_set_h_gr (current_cpu, abuf);
+      m32rx_model_profile_insn (current_cpu, abuf);
+    }
+#endif
+  return new_pc;
+#undef OPRND
+#undef FLD
+}
+
+/* Perform sll: sll $dr,$sr.  */
+CIA
+SEM_FN_NAME (m32rx,sll) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_0_add.f
+#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_0_add.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  CIA new_pc = SEM_NEXT_PC (sem_arg);
+  CPU (h_gr[f_r1]) = SLLSI (OPRND (dr), ANDSI (OPRND (sr), 31));
+  TRACE_RESULT (current_cpu, "dr", 'x', OPRND (dr));
+#if WITH_PROFILE_MODEL_P
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      m32rx_model_mark_get_h_gr (current_cpu, abuf);
+      m32rx_model_mark_set_h_gr (current_cpu, abuf);
+      m32rx_model_profile_insn (current_cpu, abuf);
+    }
+#endif
+  return new_pc;
+#undef OPRND
+#undef FLD
+}
+
+/* Perform sll3: sll3 $dr,$sr,#$simm16.  */
+CIA
+SEM_FN_NAME (m32rx,sll3) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_5_addv3.f
+#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_5_addv3.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  CIA new_pc = SEM_NEXT_PC (sem_arg);
+  CPU (h_gr[f_r1]) = SLLSI (OPRND (sr), ANDSI (OPRND (simm16), 31));
+  TRACE_RESULT (current_cpu, "dr", 'x', OPRND (dr));
+#if WITH_PROFILE_MODEL_P
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      m32rx_model_mark_get_h_gr (current_cpu, abuf);
+      m32rx_model_mark_set_h_gr (current_cpu, abuf);
+      m32rx_model_profile_insn (current_cpu, abuf);
+    }
+#endif
+  return new_pc;
+#undef OPRND
+#undef FLD
+}
+
+/* Perform slli: slli $dr,#$uimm5.  */
+CIA
+SEM_FN_NAME (m32rx,slli) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_48_slli.f
+#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_48_slli.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  CIA new_pc = SEM_NEXT_PC (sem_arg);
+  CPU (h_gr[f_r1]) = SLLSI (OPRND (dr), OPRND (uimm5));
+  TRACE_RESULT (current_cpu, "dr", 'x', OPRND (dr));
+#if WITH_PROFILE_MODEL_P
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      m32rx_model_mark_get_h_gr (current_cpu, abuf);
+      m32rx_model_mark_set_h_gr (current_cpu, abuf);
+      m32rx_model_profile_insn (current_cpu, abuf);
+    }
+#endif
+  return new_pc;
+#undef OPRND
+#undef FLD
+}
+
+/* Perform sra: sra $dr,$sr.  */
+CIA
+SEM_FN_NAME (m32rx,sra) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_0_add.f
+#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_0_add.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  CIA new_pc = SEM_NEXT_PC (sem_arg);
+  CPU (h_gr[f_r1]) = SRASI (OPRND (dr), ANDSI (OPRND (sr), 31));
+  TRACE_RESULT (current_cpu, "dr", 'x', OPRND (dr));
+#if WITH_PROFILE_MODEL_P
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      m32rx_model_mark_get_h_gr (current_cpu, abuf);
+      m32rx_model_mark_set_h_gr (current_cpu, abuf);
+      m32rx_model_profile_insn (current_cpu, abuf);
+    }
+#endif
+  return new_pc;
+#undef OPRND
+#undef FLD
+}
+
+/* Perform sra3: sra3 $dr,$sr,#$simm16.  */
+CIA
+SEM_FN_NAME (m32rx,sra3) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_5_addv3.f
+#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_5_addv3.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  CIA new_pc = SEM_NEXT_PC (sem_arg);
+  CPU (h_gr[f_r1]) = SRASI (OPRND (sr), ANDSI (OPRND (simm16), 31));
+  TRACE_RESULT (current_cpu, "dr", 'x', OPRND (dr));
+#if WITH_PROFILE_MODEL_P
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      m32rx_model_mark_get_h_gr (current_cpu, abuf);
+      m32rx_model_mark_set_h_gr (current_cpu, abuf);
+      m32rx_model_profile_insn (current_cpu, abuf);
+    }
+#endif
+  return new_pc;
+#undef OPRND
+#undef FLD
+}
+
+/* Perform srai: srai $dr,#$uimm5.  */
+CIA
+SEM_FN_NAME (m32rx,srai) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_48_slli.f
+#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_48_slli.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  CIA new_pc = SEM_NEXT_PC (sem_arg);
+  CPU (h_gr[f_r1]) = SRASI (OPRND (dr), OPRND (uimm5));
+  TRACE_RESULT (current_cpu, "dr", 'x', OPRND (dr));
+#if WITH_PROFILE_MODEL_P
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      m32rx_model_mark_get_h_gr (current_cpu, abuf);
+      m32rx_model_mark_set_h_gr (current_cpu, abuf);
+      m32rx_model_profile_insn (current_cpu, abuf);
+    }
+#endif
+  return new_pc;
+#undef OPRND
+#undef FLD
+}
+
+/* Perform srl: srl $dr,$sr.  */
+CIA
+SEM_FN_NAME (m32rx,srl) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_0_add.f
+#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_0_add.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  CIA new_pc = SEM_NEXT_PC (sem_arg);
+  CPU (h_gr[f_r1]) = SRLSI (OPRND (dr), ANDSI (OPRND (sr), 31));
+  TRACE_RESULT (current_cpu, "dr", 'x', OPRND (dr));
+#if WITH_PROFILE_MODEL_P
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      m32rx_model_mark_get_h_gr (current_cpu, abuf);
+      m32rx_model_mark_set_h_gr (current_cpu, abuf);
+      m32rx_model_profile_insn (current_cpu, abuf);
+    }
+#endif
+  return new_pc;
+#undef OPRND
+#undef FLD
+}
+
+/* Perform srl3: srl3 $dr,$sr,#$simm16.  */
+CIA
+SEM_FN_NAME (m32rx,srl3) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_5_addv3.f
+#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_5_addv3.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  CIA new_pc = SEM_NEXT_PC (sem_arg);
+  CPU (h_gr[f_r1]) = SRLSI (OPRND (sr), ANDSI (OPRND (simm16), 31));
+  TRACE_RESULT (current_cpu, "dr", 'x', OPRND (dr));
+#if WITH_PROFILE_MODEL_P
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      m32rx_model_mark_get_h_gr (current_cpu, abuf);
+      m32rx_model_mark_set_h_gr (current_cpu, abuf);
+      m32rx_model_profile_insn (current_cpu, abuf);
+    }
+#endif
+  return new_pc;
+#undef OPRND
+#undef FLD
+}
+
+/* Perform srli: srli $dr,#$uimm5.  */
+CIA
+SEM_FN_NAME (m32rx,srli) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_48_slli.f
+#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_48_slli.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  CIA new_pc = SEM_NEXT_PC (sem_arg);
+  CPU (h_gr[f_r1]) = SRLSI (OPRND (dr), OPRND (uimm5));
+  TRACE_RESULT (current_cpu, "dr", 'x', OPRND (dr));
+#if WITH_PROFILE_MODEL_P
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      m32rx_model_mark_get_h_gr (current_cpu, abuf);
+      m32rx_model_mark_set_h_gr (current_cpu, abuf);
+      m32rx_model_profile_insn (current_cpu, abuf);
+    }
+#endif
+  return new_pc;
+#undef OPRND
+#undef FLD
+}
+
+/* Perform st: st $src1,@$src2.  */
+CIA
+SEM_FN_NAME (m32rx,st) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_17_cmp.f
+#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_17_cmp.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  CIA new_pc = SEM_NEXT_PC (sem_arg);
+SETMEMSI (current_cpu, OPRND (src2), OPRND (src1));
+  TRACE_RESULT (current_cpu, "h-memory", 'x', OPRND (h_memory));
+#if WITH_PROFILE_MODEL_P
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      m32rx_model_mark_get_h_gr (current_cpu, abuf);
+      m32rx_model_profile_insn (current_cpu, abuf);
+    }
+#endif
+  return new_pc;
+#undef OPRND
+#undef FLD
+}
+
+/* Perform st-d: st $src1,@($slo16,$src2).  */
+CIA
+SEM_FN_NAME (m32rx,st_d) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_49_st_d.f
+#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_49_st_d.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  CIA new_pc = SEM_NEXT_PC (sem_arg);
+SETMEMSI (current_cpu, ADDSI (OPRND (src2), OPRND (slo16)), OPRND (src1));
+  TRACE_RESULT (current_cpu, "h-memory", 'x', OPRND (h_memory));
+#if WITH_PROFILE_MODEL_P
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      m32rx_model_mark_get_h_gr (current_cpu, abuf);
+      m32rx_model_profile_insn (current_cpu, abuf);
+    }
+#endif
+  return new_pc;
+#undef OPRND
+#undef FLD
+}
+
+/* Perform stb: stb $src1,@$src2.  */
+CIA
+SEM_FN_NAME (m32rx,stb) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_17_cmp.f
+#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_17_cmp.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  CIA new_pc = SEM_NEXT_PC (sem_arg);
+SETMEMQI (current_cpu, OPRND (src2), OPRND (src1));
+  TRACE_RESULT (current_cpu, "h-memory", 'x', OPRND (h_memory));
+#if WITH_PROFILE_MODEL_P
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      m32rx_model_mark_get_h_gr (current_cpu, abuf);
+      m32rx_model_profile_insn (current_cpu, abuf);
+    }
+#endif
+  return new_pc;
+#undef OPRND
+#undef FLD
+}
+
+/* Perform stb-d: stb $src1,@($slo16,$src2).  */
+CIA
+SEM_FN_NAME (m32rx,stb_d) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_49_st_d.f
+#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_49_st_d.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  CIA new_pc = SEM_NEXT_PC (sem_arg);
+SETMEMQI (current_cpu, ADDSI (OPRND (src2), OPRND (slo16)), OPRND (src1));
+  TRACE_RESULT (current_cpu, "h-memory", 'x', OPRND (h_memory));
+#if WITH_PROFILE_MODEL_P
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      m32rx_model_mark_get_h_gr (current_cpu, abuf);
+      m32rx_model_profile_insn (current_cpu, abuf);
+    }
+#endif
+  return new_pc;
+#undef OPRND
+#undef FLD
+}
+
+/* Perform sth: sth $src1,@$src2.  */
+CIA
+SEM_FN_NAME (m32rx,sth) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_17_cmp.f
+#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_17_cmp.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  CIA new_pc = SEM_NEXT_PC (sem_arg);
+SETMEMHI (current_cpu, OPRND (src2), OPRND (src1));
+  TRACE_RESULT (current_cpu, "h-memory", 'x', OPRND (h_memory));
+#if WITH_PROFILE_MODEL_P
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      m32rx_model_mark_get_h_gr (current_cpu, abuf);
+      m32rx_model_profile_insn (current_cpu, abuf);
+    }
+#endif
+  return new_pc;
+#undef OPRND
+#undef FLD
+}
+
+/* Perform sth-d: sth $src1,@($slo16,$src2).  */
+CIA
+SEM_FN_NAME (m32rx,sth_d) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_49_st_d.f
+#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_49_st_d.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  CIA new_pc = SEM_NEXT_PC (sem_arg);
+SETMEMHI (current_cpu, ADDSI (OPRND (src2), OPRND (slo16)), OPRND (src1));
+  TRACE_RESULT (current_cpu, "h-memory", 'x', OPRND (h_memory));
+#if WITH_PROFILE_MODEL_P
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      m32rx_model_mark_get_h_gr (current_cpu, abuf);
+      m32rx_model_profile_insn (current_cpu, abuf);
+    }
+#endif
+  return new_pc;
+#undef OPRND
+#undef FLD
+}
+
+/* Perform st-plus: st $src1,@+$src2.  */
+CIA
+SEM_FN_NAME (m32rx,st_plus) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_17_cmp.f
+#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_17_cmp.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  CIA new_pc = SEM_NEXT_PC (sem_arg);
+do {
+  CPU (h_gr[f_r2]) = ADDSI (OPRND (src2), 4);
+  TRACE_RESULT (current_cpu, "src2", 'x', OPRND (src2));
+SETMEMSI (current_cpu, OPRND (src2), OPRND (src1));
+  TRACE_RESULT (current_cpu, "h-memory", 'x', OPRND (h_memory));
+} while (0);
+#if WITH_PROFILE_MODEL_P
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      m32rx_model_mark_get_h_gr (current_cpu, abuf);
+      m32rx_model_profile_insn (current_cpu, abuf);
+    }
+#endif
+  return new_pc;
+#undef OPRND
+#undef FLD
+}
+
+/* Perform st-minus: st $src1,@-$src2.  */
+CIA
+SEM_FN_NAME (m32rx,st_minus) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_17_cmp.f
+#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_17_cmp.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  CIA new_pc = SEM_NEXT_PC (sem_arg);
+do {
+  CPU (h_gr[f_r2]) = SUBSI (OPRND (src2), 4);
+  TRACE_RESULT (current_cpu, "src2", 'x', OPRND (src2));
+SETMEMSI (current_cpu, OPRND (src2), OPRND (src1));
+  TRACE_RESULT (current_cpu, "h-memory", 'x', OPRND (h_memory));
+} while (0);
+#if WITH_PROFILE_MODEL_P
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      m32rx_model_mark_get_h_gr (current_cpu, abuf);
+      m32rx_model_profile_insn (current_cpu, abuf);
+    }
+#endif
+  return new_pc;
+#undef OPRND
+#undef FLD
+}
+
+/* Perform sub: sub $dr,$sr.  */
+CIA
+SEM_FN_NAME (m32rx,sub) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_0_add.f
+#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_0_add.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  CIA new_pc = SEM_NEXT_PC (sem_arg);
+  CPU (h_gr[f_r1]) = SUBSI (OPRND (dr), OPRND (sr));
+  TRACE_RESULT (current_cpu, "dr", 'x', OPRND (dr));
+#if WITH_PROFILE_MODEL_P
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      m32rx_model_mark_get_h_gr (current_cpu, abuf);
+      m32rx_model_mark_set_h_gr (current_cpu, abuf);
+      m32rx_model_profile_insn (current_cpu, abuf);
+    }
+#endif
+  return new_pc;
+#undef OPRND
+#undef FLD
+}
+
+/* Perform subv: subv $dr,$sr.  */
+CIA
+SEM_FN_NAME (m32rx,subv) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_0_add.f
+#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_0_add.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  CIA new_pc = SEM_NEXT_PC (sem_arg);
+do {
+  BI temp1;SI temp0;
+  temp0 = SUBSI (OPRND (dr), OPRND (sr));
+  temp1 = SUBOFSI (OPRND (dr), OPRND (sr), 0);
+  CPU (h_gr[f_r1]) = temp0;
+  TRACE_RESULT (current_cpu, "dr", 'x', OPRND (dr));
+  CPU (h_cond) = temp1;
+  TRACE_RESULT (current_cpu, "condbit", 'x', OPRND (condbit));
+} while (0);
+#if WITH_PROFILE_MODEL_P
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      m32rx_model_mark_get_h_gr (current_cpu, abuf);
+      m32rx_model_mark_set_h_gr (current_cpu, abuf);
+      m32rx_model_profile_insn (current_cpu, abuf);
+    }
+#endif
+  return new_pc;
+#undef OPRND
+#undef FLD
+}
+
+/* Perform subx: subx $dr,$sr.  */
+CIA
+SEM_FN_NAME (m32rx,subx) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_6_addx.f
+#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_6_addx.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  CIA new_pc = SEM_NEXT_PC (sem_arg);
+do {
+  BI temp1;SI temp0;
+  temp0 = SUBCSI (OPRND (dr), OPRND (sr), OPRND (condbit));
+  temp1 = SUBCFSI (OPRND (dr), OPRND (sr), OPRND (condbit));
+  CPU (h_gr[f_r1]) = temp0;
+  TRACE_RESULT (current_cpu, "dr", 'x', OPRND (dr));
+  CPU (h_cond) = temp1;
+  TRACE_RESULT (current_cpu, "condbit", 'x', OPRND (condbit));
+} while (0);
+#if WITH_PROFILE_MODEL_P
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      m32rx_model_mark_get_h_gr (current_cpu, abuf);
+      m32rx_model_mark_set_h_gr (current_cpu, abuf);
+      m32rx_model_profile_insn (current_cpu, abuf);
+    }
+#endif
+  return new_pc;
+#undef OPRND
+#undef FLD
+}
+
+/* Perform trap: trap #$uimm4.  */
+CIA
+SEM_FN_NAME (m32rx,trap) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_50_trap.f
+#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_50_trap.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  CIA new_pc = SEM_NEXT_PC (sem_arg);
+  int taken_p = 0;
+do_trap (current_cpu, OPRND (uimm4));
+#if WITH_PROFILE_MODEL_P
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      m32rx_model_profile_cti_insn (current_cpu, abuf, taken_p);
+    }
+#endif
+  return new_pc;
+#undef OPRND
+#undef FLD
+}
+
+/* Perform unlock: unlock $src1,@$src2.  */
+CIA
+SEM_FN_NAME (m32rx,unlock) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_17_cmp.f
+#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_17_cmp.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  CIA new_pc = SEM_NEXT_PC (sem_arg);
+do_unlock (current_cpu, OPRND (src1), OPRND (src2));
+#if WITH_PROFILE_MODEL_P
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      m32rx_model_mark_get_h_gr (current_cpu, abuf);
+      m32rx_model_profile_insn (current_cpu, abuf);
+    }
+#endif
+  return new_pc;
+#undef OPRND
+#undef FLD
+}
+
+/* Perform satb: satb $dr,$src2.  */
+CIA
+SEM_FN_NAME (m32rx,satb) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_51_satb.f
+#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_51_satb.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  CIA new_pc = SEM_NEXT_PC (sem_arg);
+  CPU (h_gr[f_r1]) = (GESI (OPRND (src2), 127)) ? (127) : (LESI (OPRND (src2), -128)) ? (-128) : (OPRND (src2));
+  TRACE_RESULT (current_cpu, "dr", 'x', OPRND (dr));
+#if WITH_PROFILE_MODEL_P
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      m32rx_model_mark_set_h_gr (current_cpu, abuf);
+      m32rx_model_profile_insn (current_cpu, abuf);
+    }
+#endif
+  return new_pc;
+#undef OPRND
+#undef FLD
+}
+
+/* Perform sath: sath $dr,$src2.  */
+CIA
+SEM_FN_NAME (m32rx,sath) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_51_satb.f
+#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_51_satb.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  CIA new_pc = SEM_NEXT_PC (sem_arg);
+  CPU (h_gr[f_r1]) = (GESI (OPRND (src2), 32767)) ? (32767) : (LESI (OPRND (src2), -32768)) ? (-32768) : (OPRND (src2));
+  TRACE_RESULT (current_cpu, "dr", 'x', OPRND (dr));
+#if WITH_PROFILE_MODEL_P
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      m32rx_model_mark_set_h_gr (current_cpu, abuf);
+      m32rx_model_profile_insn (current_cpu, abuf);
+    }
+#endif
+  return new_pc;
+#undef OPRND
+#undef FLD
+}
+
+/* Perform sat: sat $dr,$src2.  */
+CIA
+SEM_FN_NAME (m32rx,sat) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_51_satb.f
+#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_51_satb.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  CIA new_pc = SEM_NEXT_PC (sem_arg);
+  CPU (h_gr[f_r1]) = (OPRND (condbit)) ? ((LTSI (OPRND (src2), 0)) ? (2147483647) : (0x80000000)) : (OPRND (src2));
+  TRACE_RESULT (current_cpu, "dr", 'x', OPRND (dr));
+#if WITH_PROFILE_MODEL_P
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      m32rx_model_mark_set_h_gr (current_cpu, abuf);
+      m32rx_model_profile_insn (current_cpu, abuf);
+    }
+#endif
+  return new_pc;
+#undef OPRND
+#undef FLD
+}
+
+/* Perform pcmpbz: pcmpbz $src2.  */
+CIA
+SEM_FN_NAME (m32rx,pcmpbz) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_52_pcmpbz.f
+#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_52_pcmpbz.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  CIA new_pc = SEM_NEXT_PC (sem_arg);
+  CPU (h_cond) = (EQSI (ANDSI (OPRND (src2), 255), 0)) ? (1) : (EQSI (ANDSI (OPRND (src2), 65280), 0)) ? (1) : (EQSI (ANDSI (OPRND (src2), 16711680), 0)) ? (1) : (EQSI (ANDSI (OPRND (src2), 0xff000000), 0)) ? (1) : (0);
+  TRACE_RESULT (current_cpu, "condbit", 'x', OPRND (condbit));
+#if WITH_PROFILE_MODEL_P
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      m32rx_model_profile_insn (current_cpu, abuf);
+    }
+#endif
+  return new_pc;
+#undef OPRND
+#undef FLD
+}
+
+/* Perform sadd: sadd.  */
+CIA
+SEM_FN_NAME (m32rx,sadd) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_53_sadd.f
+#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_53_sadd.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  CIA new_pc = SEM_NEXT_PC (sem_arg);
+m32rx_h_accums_set (current_cpu, 0, ADDDI (SRADI (OPRND (h_accums), 16), OPRND (h_accums)));
+  TRACE_RESULT (current_cpu, "h-accums", 'D', OPRND (h_accums));
+#if WITH_PROFILE_MODEL_P
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      m32rx_model_profile_insn (current_cpu, abuf);
+    }
+#endif
+  return new_pc;
+#undef OPRND
+#undef FLD
+}
+
+/* Perform macwu1: macwu1 $src1,$src2.  */
+CIA
+SEM_FN_NAME (m32rx,macwu1) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_54_macwu1.f
+#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_54_macwu1.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  CIA new_pc = SEM_NEXT_PC (sem_arg);
+m32rx_h_accums_set (current_cpu, 1, SRADI (SLLDI (ADDDI (OPRND (h_accums), MULDI (EXTSIDI (OPRND (src1)), EXTSIDI (ANDSI (OPRND (src2), 65535)))), 8), 8));
+  TRACE_RESULT (current_cpu, "h-accums", 'D', OPRND (h_accums));
+#if WITH_PROFILE_MODEL_P
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      m32rx_model_mark_get_h_gr (current_cpu, abuf);
+      m32rx_model_profile_insn (current_cpu, abuf);
+    }
+#endif
+  return new_pc;
+#undef OPRND
+#undef FLD
+}
+
+/* Perform msblo: msblo $src1,$src2.  */
+CIA
+SEM_FN_NAME (m32rx,msblo) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_34_machi.f
+#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_34_machi.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  CIA new_pc = SEM_NEXT_PC (sem_arg);
+  CPU (h_accum) = SRADI (SLLDI (SUBDI (OPRND (accum), SRADI (SLLDI (MULDI (EXTHIDI (TRUNCSIHI (OPRND (src1))), EXTHIDI (TRUNCSIHI (OPRND (src2)))), 32), 16)), 8), 8);
+  TRACE_RESULT (current_cpu, "accum", 'D', OPRND (accum));
+#if WITH_PROFILE_MODEL_P
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      m32rx_model_mark_get_h_gr (current_cpu, abuf);
+      m32rx_model_profile_insn (current_cpu, abuf);
+    }
+#endif
+  return new_pc;
+#undef OPRND
+#undef FLD
+}
+
+/* Perform mulwu1: mulwu1 $src1,$src2.  */
+CIA
+SEM_FN_NAME (m32rx,mulwu1) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_17_cmp.f
+#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_17_cmp.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  CIA new_pc = SEM_NEXT_PC (sem_arg);
+m32rx_h_accums_set (current_cpu, 1, SRADI (SLLDI (MULDI (EXTSIDI (OPRND (src1)), EXTSIDI (ANDSI (OPRND (src2), 65535))), 16), 16));
+  TRACE_RESULT (current_cpu, "h-accums", 'D', OPRND (h_accums));
+#if WITH_PROFILE_MODEL_P
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      m32rx_model_mark_get_h_gr (current_cpu, abuf);
+      m32rx_model_profile_insn (current_cpu, abuf);
+    }
+#endif
+  return new_pc;
+#undef OPRND
+#undef FLD
+}
+
+/* Perform machl1: machl1 $src1,$src2.  */
+CIA
+SEM_FN_NAME (m32rx,machl1) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_54_macwu1.f
+#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_54_macwu1.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  CIA new_pc = SEM_NEXT_PC (sem_arg);
+m32rx_h_accums_set (current_cpu, 1, SRADI (SLLDI (ADDDI (OPRND (h_accums), SRADI (SLLDI (MULDI (EXTSIDI (SRASI (OPRND (src1), 16)), EXTHIDI (TRUNCSIHI (OPRND (src2)))), 32), 16)), 8), 8));
+  TRACE_RESULT (current_cpu, "h-accums", 'D', OPRND (h_accums));
+#if WITH_PROFILE_MODEL_P
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      m32rx_model_mark_get_h_gr (current_cpu, abuf);
+      m32rx_model_profile_insn (current_cpu, abuf);
+    }
+#endif
+  return new_pc;
+#undef OPRND
+#undef FLD
+}
+
+/* Perform sc: sc.  */
+CIA
+SEM_FN_NAME (m32rx,sc) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_55_sc.f
+#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_55_sc.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  CIA new_pc = SEM_NEXT_PC (sem_arg);
+if (OPRND (condbit)) {
+  CPU (h_abort) = 1;
+  TRACE_RESULT (current_cpu, "abort-parallel-execution", 'x', OPRND (abort_parallel_execution));
+}
+#if WITH_PROFILE_MODEL_P
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      m32rx_model_profile_insn (current_cpu, abuf);
+    }
+#endif
+  return new_pc;
+#undef OPRND
+#undef FLD
+}
+
+/* Perform snc: snc.  */
+CIA
+SEM_FN_NAME (m32rx,snc) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_55_sc.f
+#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_55_sc.f
+  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+  CIA new_pc = SEM_NEXT_PC (sem_arg);
+if (NOTBI (OPRND (condbit))) {
+  CPU (h_abort) = 1;
+  TRACE_RESULT (current_cpu, "abort-parallel-execution", 'x', OPRND (abort_parallel_execution));
+}
+#if WITH_PROFILE_MODEL_P
+  if (PROFILE_MODEL_P (current_cpu))
+    {
+      m32rx_model_profile_insn (current_cpu, abuf);
+    }
+#endif
+  return new_pc;
+#undef OPRND
+#undef FLD
+}
+
+/* FIXME: Add "no return" attribute to illegal insn handlers.
+   They all call longjmp.  */
+
+PCADDR
+SEM_FN_NAME (m32rx,illegal) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+  sim_engine_illegal_insn (current_cpu, NULL_CIA /*FIXME*/);
+  return 0;
+}
+
+#endif /* ! defined (SCACHE_P) || (defined (SCACHE_P) && WITH_SCACHE) */