From: Xiang, Haihao Date: Tue, 29 Jan 2008 03:13:53 +0000 (+0800) Subject: i965: new integrated graphics chipset support X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=8e444fb9e2685e3eac42beb848b08e91dc20c88a;p=mesa.git i965: new integrated graphics chipset support --- diff --git a/src/mesa/drivers/dri/i965/brw_clip.c b/src/mesa/drivers/dri/i965/brw_clip.c index e6f3f631264..24b0288f887 100644 --- a/src/mesa/drivers/dri/i965/brw_clip.c +++ b/src/mesa/drivers/dri/i965/brw_clip.c @@ -60,7 +60,7 @@ static void compile_clip_prog( struct brw_context *brw, /* Begin the compilation: */ - brw_init_compile(&c.func); + brw_init_compile(brw, &c.func); c.func.single_program_flow = 1; diff --git a/src/mesa/drivers/dri/i965/brw_clip_line.c b/src/mesa/drivers/dri/i965/brw_clip_line.c index 9ad00676d4b..7d51cddfc3d 100644 --- a/src/mesa/drivers/dri/i965/brw_clip_line.c +++ b/src/mesa/drivers/dri/i965/brw_clip_line.c @@ -148,10 +148,13 @@ static void clip_and_emit_line( struct brw_clip_compile *c ) brw_clip_init_clipmask(c); /* -ve rhw workaround */ - brw_set_conditionalmod(p, BRW_CONDITIONAL_NZ); - brw_AND(p, brw_null_reg(), get_element_ud(c->reg.R0, 2), - brw_imm_ud(1<<20)); - brw_OR(p, c->reg.planemask, c->reg.planemask, brw_imm_ud(0x3f)); + if (!BRW_IS_IGD(p->brw)) { + brw_set_conditionalmod(p, BRW_CONDITIONAL_NZ); + brw_AND(p, brw_null_reg(), get_element_ud(c->reg.R0, 2), + brw_imm_ud(1<<20)); + brw_OR(p, c->reg.planemask, c->reg.planemask, brw_imm_ud(0x3f)); + } + brw_set_predicate_control(p, BRW_PREDICATE_NONE); plane_loop = brw_DO(p, BRW_EXECUTE_1); diff --git a/src/mesa/drivers/dri/i965/brw_clip_state.c b/src/mesa/drivers/dri/i965/brw_clip_state.c index 0b0634ec78b..cbf9cdcfce8 100644 --- a/src/mesa/drivers/dri/i965/brw_clip_state.c +++ b/src/mesa/drivers/dri/i965/brw_clip_state.c @@ -101,6 +101,10 @@ clip_unit_create_from_key(struct brw_context *brw, clip.clip5.vertex_position_space = BRW_CLIP_NDCSPACE; clip.clip5.api_mode = BRW_CLIP_API_OGL; clip.clip5.clip_mode = key->clip_mode; + + if (BRW_IS_IGD(brw)) + clip.clip5.negative_w_clip_test = 1; + clip.clip6.clipper_viewport_state_ptr = 0; clip.viewport_xmin = -1; clip.viewport_xmax = 1; diff --git a/src/mesa/drivers/dri/i965/brw_clip_tri.c b/src/mesa/drivers/dri/i965/brw_clip_tri.c index 316dab80706..f1fc6e1e9da 100644 --- a/src/mesa/drivers/dri/i965/brw_clip_tri.c +++ b/src/mesa/drivers/dri/i965/brw_clip_tri.c @@ -536,15 +536,16 @@ void brw_emit_tri_clip( struct brw_clip_compile *c ) /* if -ve rhw workaround bit is set, do cliptest */ - brw_set_conditionalmod(p, BRW_CONDITIONAL_NZ); - brw_AND(p, brw_null_reg(), get_element_ud(c->reg.R0, 2), - brw_imm_ud(1<<20)); - neg_rhw = brw_IF(p, BRW_EXECUTE_1); - { - brw_clip_test(c); + if (!BRW_IS_IGD(p->brw)) { + brw_set_conditionalmod(p, BRW_CONDITIONAL_NZ); + brw_AND(p, brw_null_reg(), get_element_ud(c->reg.R0, 2), + brw_imm_ud(1<<20)); + neg_rhw = brw_IF(p, BRW_EXECUTE_1); + { + brw_clip_test(c); + } + brw_ENDIF(p, neg_rhw); } - brw_ENDIF(p, neg_rhw); - /* Can't push into do_clip_tri because with polygon (or quad) * flatshading, need to apply the flatshade here because we don't * respect the PV when converting to trifan for emit: diff --git a/src/mesa/drivers/dri/i965/brw_defines.h b/src/mesa/drivers/dri/i965/brw_defines.h index 9bb7d2f703d..d37931c0822 100644 --- a/src/mesa/drivers/dri/i965/brw_defines.h +++ b/src/mesa/drivers/dri/i965/brw_defines.h @@ -817,14 +817,16 @@ #define CMD_STATE_BASE_ADDRESS 0x6101 #define CMD_STATE_INSN_POINTER 0x6102 -#define CMD_PIPELINE_SELECT 0x6104 +#define CMD_PIPELINE_SELECT_965 0x6104 +#define CMD_PIPELINE_SELECT_IGD 0x6904 #define CMD_PIPELINED_STATE_POINTERS 0x7800 #define CMD_BINDING_TABLE_PTRS 0x7801 #define CMD_VERTEX_BUFFER 0x7808 #define CMD_VERTEX_ELEMENT 0x7809 #define CMD_INDEX_BUFFER 0x780a -#define CMD_VF_STATISTICS 0x780b +#define CMD_VF_STATISTICS_965 0x780b +#define CMD_VF_STATISTICS_IGD 0x680b #define CMD_DRAW_RECT 0x7900 #define CMD_BLEND_CONSTANT_COLOR 0x7901 @@ -834,6 +836,7 @@ #define CMD_POLY_STIPPLE_PATTERN 0x7907 #define CMD_LINE_STIPPLE_PATTERN 0x7908 #define CMD_GLOBAL_DEPTH_OFFSET_CLAMP 0x7909 +#define CMD_AA_LINE_PARAMETERS 0x790a #define CMD_PIPE_CONTROL 0x7a00 @@ -847,6 +850,11 @@ #define R02_PRIM_END 0x1 #define R02_PRIM_START 0x2 +#include "intel_chipset.h" +#define BRW_IS_IGD(brw) (IS_IGD((brw)->intel.intelScreen->deviceID)) +#define CMD_PIPELINE_SELECT(brw) ((BRW_IS_IGD(brw)) ? CMD_PIPELINE_SELECT_IGD : CMD_PIPELINE_SELECT_965) +#define CMD_VF_STATISTICS(brw) ((BRW_IS_IGD(brw)) ? CMD_VF_STATISTICS_IGD : CMD_VF_STATISTICS_965) +#define URB_SIZES(brw) ((BRW_IS_IGD(brw)) ? 384 : 256) /* 512 bit unit */ #endif diff --git a/src/mesa/drivers/dri/i965/brw_eu.c b/src/mesa/drivers/dri/i965/brw_eu.c index d1244befd78..b3ae4eef334 100644 --- a/src/mesa/drivers/dri/i965/brw_eu.c +++ b/src/mesa/drivers/dri/i965/brw_eu.c @@ -101,8 +101,9 @@ void brw_pop_insn_state( struct brw_compile *p ) /*********************************************************************** */ -void brw_init_compile( struct brw_compile *p ) +void brw_init_compile( struct brw_context *brw, struct brw_compile *p ) { + p->brw = brw; p->nr_insn = 0; p->current = p->stack; memset(p->current, 0, sizeof(p->current[0])); diff --git a/src/mesa/drivers/dri/i965/brw_eu.h b/src/mesa/drivers/dri/i965/brw_eu.h index 5ef8fef09df..25f1f896f7d 100644 --- a/src/mesa/drivers/dri/i965/brw_eu.h +++ b/src/mesa/drivers/dri/i965/brw_eu.h @@ -105,6 +105,7 @@ struct brw_compile { GLuint flag_value; GLboolean single_program_flow; + struct brw_context *brw; }; @@ -693,7 +694,7 @@ void brw_set_predicate_control_flag_value( struct brw_compile *p, GLuint value ) void brw_set_predicate_control( struct brw_compile *p, GLuint pc ); void brw_set_conditionalmod( struct brw_compile *p, GLuint conditional ); -void brw_init_compile( struct brw_compile *p ); +void brw_init_compile( struct brw_context *, struct brw_compile *p ); const GLuint *brw_get_program( struct brw_compile *p, GLuint *sz ); diff --git a/src/mesa/drivers/dri/i965/brw_eu_emit.c b/src/mesa/drivers/dri/i965/brw_eu_emit.c index 284307341cb..fefd30bc7f5 100644 --- a/src/mesa/drivers/dri/i965/brw_eu_emit.c +++ b/src/mesa/drivers/dri/i965/brw_eu_emit.c @@ -318,7 +318,8 @@ static void brw_set_dp_read_message( struct brw_instruction *insn, insn->bits3.dp_read.end_of_thread = end_of_thread; } -static void brw_set_sampler_message( struct brw_instruction *insn, +static void brw_set_sampler_message(struct brw_context *brw, + struct brw_instruction *insn, GLuint binding_table_index, GLuint sampler, GLuint msg_type, @@ -328,14 +329,24 @@ static void brw_set_sampler_message( struct brw_instruction *insn, { brw_set_src1(insn, brw_imm_d(0)); - insn->bits3.sampler.binding_table_index = binding_table_index; - insn->bits3.sampler.sampler = sampler; - insn->bits3.sampler.msg_type = msg_type; - insn->bits3.sampler.return_format = BRW_SAMPLER_RETURN_FORMAT_FLOAT32; - insn->bits3.sampler.response_length = response_length; - insn->bits3.sampler.msg_length = msg_length; - insn->bits3.sampler.end_of_thread = eot; - insn->bits3.sampler.msg_target = BRW_MESSAGE_TARGET_SAMPLER; + if (BRW_IS_IGD(brw)) { + insn->bits3.sampler_igd.binding_table_index = binding_table_index; + insn->bits3.sampler_igd.sampler = sampler; + insn->bits3.sampler_igd.msg_type = msg_type; + insn->bits3.sampler_igd.response_length = response_length; + insn->bits3.sampler_igd.msg_length = msg_length; + insn->bits3.sampler_igd.end_of_thread = eot; + insn->bits3.sampler_igd.msg_target = BRW_MESSAGE_TARGET_SAMPLER; + } else { + insn->bits3.sampler.binding_table_index = binding_table_index; + insn->bits3.sampler.sampler = sampler; + insn->bits3.sampler.msg_type = msg_type; + insn->bits3.sampler.return_format = BRW_SAMPLER_RETURN_FORMAT_FLOAT32; + insn->bits3.sampler.response_length = response_length; + insn->bits3.sampler.msg_length = msg_length; + insn->bits3.sampler.end_of_thread = eot; + insn->bits3.sampler.msg_target = BRW_MESSAGE_TARGET_SAMPLER; + } } @@ -1017,7 +1028,7 @@ void brw_SAMPLE(struct brw_compile *p, brw_set_dest(insn, dest); brw_set_src0(insn, src0); - brw_set_sampler_message(insn, + brw_set_sampler_message(p->brw, insn, binding_table_index, sampler, msg_type, diff --git a/src/mesa/drivers/dri/i965/brw_gs.c b/src/mesa/drivers/dri/i965/brw_gs.c index 5c52212a3b0..922a3ba3a51 100644 --- a/src/mesa/drivers/dri/i965/brw_gs.c +++ b/src/mesa/drivers/dri/i965/brw_gs.c @@ -65,7 +65,7 @@ static void compile_gs_prog( struct brw_context *brw, /* Begin the compilation: */ - brw_init_compile(&c.func); + brw_init_compile(brw, &c.func); c.func.single_program_flow = 1; diff --git a/src/mesa/drivers/dri/i965/brw_misc_state.c b/src/mesa/drivers/dri/i965/brw_misc_state.c index acc19f77670..8277da7dd30 100644 --- a/src/mesa/drivers/dri/i965/brw_misc_state.c +++ b/src/mesa/drivers/dri/i965/brw_misc_state.c @@ -182,15 +182,20 @@ static void upload_depthbuffer(struct brw_context *brw) { struct intel_context *intel = &brw->intel; struct intel_region *region = brw->state.depth_region; + unsigned int len = BRW_IS_IGD(brw) ? sizeof(struct brw_depthbuffer_igd) / 4 : sizeof(struct brw_depthbuffer) / 4; if (region == NULL) { - BEGIN_BATCH(5, IGNORE_CLIPRECTS); - OUT_BATCH(CMD_DEPTH_BUFFER << 16 | (5 - 2)); + BEGIN_BATCH(len, IGNORE_CLIPRECTS); + OUT_BATCH(CMD_DEPTH_BUFFER << 16 | (len - 2)); OUT_BATCH((BRW_DEPTHFORMAT_D32_FLOAT << 18) | (BRW_SURFACE_NULL << 29)); OUT_BATCH(0); OUT_BATCH(0); OUT_BATCH(0); + + if (BRW_IS_IGD(brw)) + OUT_BATCH(0); + ADVANCE_BATCH(); } else { unsigned int format; @@ -210,8 +215,8 @@ static void upload_depthbuffer(struct brw_context *brw) return; } - BEGIN_BATCH(5, IGNORE_CLIPRECTS); - OUT_BATCH(CMD_DEPTH_BUFFER << 16 | (5 - 2)); + BEGIN_BATCH(len, IGNORE_CLIPRECTS); + OUT_BATCH(CMD_DEPTH_BUFFER << 16 | (len - 2)); OUT_BATCH(((region->pitch * region->cpp) - 1) | (format << 18) | (BRW_TILEWALK_YMAJOR << 26) | @@ -223,6 +228,10 @@ static void upload_depthbuffer(struct brw_context *brw) ((region->pitch - 1) << 6) | ((region->height - 1) << 19)); OUT_BATCH(0); + + if (BRW_IS_IGD(brw)) + OUT_BATCH(0); + ADVANCE_BATCH(); } } @@ -295,6 +304,33 @@ const struct brw_tracked_state brw_polygon_stipple_offset = { .update = upload_polygon_stipple_offset }; +/********************************************************************** + * AA Line parameters + */ +static void upload_aa_line_parameters(struct brw_context *brw) +{ + struct brw_aa_line_parameters balp; + + if (!BRW_IS_IGD(brw)) + return; + + /* use legacy aa line coverage computation */ + memset(&balp, 0, sizeof(balp)); + balp.header.opcode = CMD_AA_LINE_PARAMETERS; + balp.header.length = sizeof(balp) / 4 - 2; + + BRW_CACHED_BATCH_STRUCT(brw, &balp); +} + +const struct brw_tracked_state brw_aa_line_parameters = { + .dirty = { + .mesa = 0, + .brw = BRW_NEW_CONTEXT, + .cache = 0 + }, + .update = upload_aa_line_parameters +}; + /*********************************************************************** * Line stipple packet */ @@ -377,7 +413,7 @@ static void upload_invarient_state( struct brw_context *brw ) struct brw_pipeline_select ps; memset(&ps, 0, sizeof(ps)); - ps.header.opcode = CMD_PIPELINE_SELECT; + ps.header.opcode = CMD_PIPELINE_SELECT(brw); ps.header.pipeline_select = 0; BRW_BATCH_STRUCT(brw, &ps); } @@ -413,7 +449,7 @@ static void upload_invarient_state( struct brw_context *brw ) struct brw_vf_statistics vfs; memset(&vfs, 0, sizeof(vfs)); - vfs.opcode = CMD_VF_STATISTICS; + vfs.opcode = CMD_VF_STATISTICS(brw); if (INTEL_DEBUG & DEBUG_STATS) vfs.statistics_enable = 1; diff --git a/src/mesa/drivers/dri/i965/brw_sf.c b/src/mesa/drivers/dri/i965/brw_sf.c index 6c2f174bf5d..9250dc36e6d 100644 --- a/src/mesa/drivers/dri/i965/brw_sf.c +++ b/src/mesa/drivers/dri/i965/brw_sf.c @@ -57,7 +57,7 @@ static void compile_sf_prog( struct brw_context *brw, /* Begin the compilation: */ - brw_init_compile(&c.func); + brw_init_compile(brw, &c.func); c.key = *key; c.nr_attrs = brw_count_bits(c.key.attrs); diff --git a/src/mesa/drivers/dri/i965/brw_sf_state.c b/src/mesa/drivers/dri/i965/brw_sf_state.c index f083e3148b1..2b6087d6915 100644 --- a/src/mesa/drivers/dri/i965/brw_sf_state.c +++ b/src/mesa/drivers/dri/i965/brw_sf_state.c @@ -230,6 +230,7 @@ sf_unit_create_from_key(struct brw_context *brw, struct brw_sf_unit_key *key, sf.sf7.sprite_point = key->point_sprite; sf.sf7.point_size = CLAMP(key->point_size, 1.0, 255.0) * (1<<3); sf.sf7.use_point_size_state = !key->point_attenuated; + sf.sf7.aa_line_distance_mode = 0; /* might be BRW_NEW_PRIMITIVE if we have to adjust pv for polygons: */ diff --git a/src/mesa/drivers/dri/i965/brw_state.h b/src/mesa/drivers/dri/i965/brw_state.h index 66755cabaf2..1510e5b0425 100644 --- a/src/mesa/drivers/dri/i965/brw_state.h +++ b/src/mesa/drivers/dri/i965/brw_state.h @@ -49,6 +49,7 @@ const struct brw_tracked_state brw_invarient_state; const struct brw_tracked_state brw_gs_prog; const struct brw_tracked_state brw_gs_unit; const struct brw_tracked_state brw_line_stipple; +const struct brw_tracked_state brw_aa_line_parameters; const struct brw_tracked_state brw_pipelined_state_pointers; const struct brw_tracked_state brw_binding_table_pointers; const struct brw_tracked_state brw_depthbuffer; diff --git a/src/mesa/drivers/dri/i965/brw_state_upload.c b/src/mesa/drivers/dri/i965/brw_state_upload.c index 1c818a2cb2d..d35f94e620d 100644 --- a/src/mesa/drivers/dri/i965/brw_state_upload.c +++ b/src/mesa/drivers/dri/i965/brw_state_upload.c @@ -91,7 +91,7 @@ const struct brw_tracked_state *atoms[] = &brw_polygon_stipple_offset, &brw_line_stipple, - + &brw_aa_line_parameters, /* Ordering of the commands below is documented as fixed. */ #if 0 diff --git a/src/mesa/drivers/dri/i965/brw_structs.h b/src/mesa/drivers/dri/i965/brw_structs.h index dd11640e6bf..1326280e00a 100644 --- a/src/mesa/drivers/dri/i965/brw_structs.h +++ b/src/mesa/drivers/dri/i965/brw_structs.h @@ -141,7 +141,8 @@ struct brw_depthbuffer struct { GLuint pitch:18; GLuint format:3; - GLuint pad:4; + GLuint pad:2; + GLuint software_tiled_rendering_mode:2; GLuint depth_offset_disable:1; GLuint tile_walk:1; GLuint tiled_surface:1; @@ -166,14 +167,64 @@ struct brw_depthbuffer union { struct { - GLuint pad:12; - GLuint min_array_element:9; + GLuint pad:10; + GLuint min_array_element:11; GLuint depth:11; } bits; GLuint dword; } dword4; }; +struct brw_depthbuffer_igd +{ + union header_union header; + + union { + struct { + GLuint pitch:18; + GLuint format:3; + GLuint pad:2; + GLuint software_tiled_rendering_mode:2; + GLuint depth_offset_disable:1; + GLuint tile_walk:1; + GLuint tiled_surface:1; + GLuint pad2:1; + GLuint surface_type:3; + } bits; + GLuint dword; + } dword1; + + GLuint dword2_base_addr; + + union { + struct { + GLuint pad:1; + GLuint mipmap_layout:1; + GLuint lod:4; + GLuint width:13; + GLuint height:13; + } bits; + GLuint dword; + } dword3; + + union { + struct { + GLuint pad:10; + GLuint min_array_element:11; + GLuint depth:11; + } bits; + GLuint dword; + } dword4; + + union { + struct { + GLuint xoffset:16; + GLuint yoffset:16; + } bits; + GLuint dword; + } dword5; /* NEW in Integrated Graphics Device */ +}; + struct brw_drawrect { struct header header; @@ -213,6 +264,25 @@ struct brw_indexbuffer GLuint buffer_end; }; +/* NEW in Integrated Graphics Device */ +struct brw_aa_line_parameters +{ + struct header header; + + struct { + GLuint aa_coverage_scope:8; + GLuint pad0:8; + GLuint aa_coverage_bias:8; + GLuint pad1:8; + } bits0; + + struct { + GLuint aa_coverage_endcap_slope:8; + GLuint pad0:8; + GLuint aa_coverage_endcap_bias:8; + GLuint pad1:8; + } bits1; +}; struct brw_line_stipple { @@ -315,7 +385,8 @@ struct brw_pipe_control { GLuint length:8; GLuint notify_enable:1; - GLuint pad:2; + GLuint texture_cache_flush_enable:1; + GLuint indirect_state_pointers_disable:1; GLuint instruction_state_cache_flush_enable:1; GLuint write_cache_flush_enable:1; GLuint depth_stall_enable:1; @@ -547,8 +618,8 @@ struct brw_clip_unit_state GLuint pad1:1; GLuint urb_entry_allocation_size:5; GLuint pad2:1; - GLuint max_threads:1; /* may be less */ - GLuint pad3:6; + GLuint max_threads:5; /* may be less */ + GLuint pad3:2; } thread4; struct @@ -557,7 +628,7 @@ struct brw_clip_unit_state GLuint clip_mode:3; GLuint userclip_enable_flags:8; GLuint userclip_must_clip:1; - GLuint pad1:1; + GLuint negative_w_clip_test:1; GLuint guard_band_enable:1; GLuint viewport_z_clip_enable:1; GLuint viewport_xy_clip_enable:1; @@ -724,7 +795,8 @@ struct brw_sf_unit_state GLuint use_point_size_state:1; GLuint subpixel_precision:1; GLuint sprite_point:1; - GLuint pad0:11; + GLuint pad0:10; + GLuint aa_line_distance_mode:1; GLuint trifan_pv:2; GLuint linestrip_pv:2; GLuint tristrip_pv:2; @@ -749,8 +821,8 @@ struct brw_gs_unit_state GLuint pad1:1; GLuint urb_entry_allocation_size:5; GLuint pad2:1; - GLuint max_threads:1; - GLuint pad3:6; + GLuint max_threads:5; + GLuint pad3:2; } thread4; struct @@ -764,9 +836,14 @@ struct brw_gs_unit_state struct { GLuint max_vp_index:4; - GLuint pad0:26; - GLuint reorder_enable:1; + GLuint pad0:12; + GLuint svbi_post_inc_value:10; GLuint pad1:1; + GLuint svbi_post_inc_enable:1; + GLuint svbi_payload:1; + GLuint discard_adjaceny:1; + GLuint reorder_enable:1; + GLuint pad2:1; } gs6; }; @@ -786,8 +863,8 @@ struct brw_vs_unit_state GLuint pad1:1; GLuint urb_entry_allocation_size:5; GLuint pad2:1; - GLuint max_threads:4; - GLuint pad3:3; + GLuint max_threads:6; + GLuint pad3:1; } thread4; struct @@ -815,7 +892,7 @@ struct brw_wm_unit_state struct { GLuint stats_enable:1; - GLuint pad0:1; + GLuint depth_buffer_clear:1; GLuint sampler_count:3; GLuint sampler_state_pointer:27; } wm4; @@ -825,7 +902,9 @@ struct brw_wm_unit_state GLuint enable_8_pix:1; GLuint enable_16_pix:1; GLuint enable_32_pix:1; - GLuint pad0:7; + GLuint enable_con_32_pix:1; + GLuint enable_con_64_pix:1; + GLuint pad0:5; GLuint legacy_global_depth_bias:1; GLuint line_stipple:1; GLuint depth_offset:1; @@ -838,9 +917,8 @@ struct brw_wm_unit_state GLuint program_computes_depth:1; GLuint program_uses_killpixel:1; GLuint legacy_line_rast: 1; - GLuint pad1:1; - GLuint max_threads:6; - GLuint pad2:1; + GLuint transposed_urb_read_enable:1; + GLuint max_threads:7; } wm5; GLfloat global_depth_offset_constant; @@ -979,10 +1057,26 @@ struct brw_surface_state } ss3; struct { - GLuint pad:19; - GLuint min_array_elt:9; + GLuint multisample_position_palette_index:3; + GLuint pad1:1; + GLuint num_multisamples:3; + GLuint pad0:1; + GLuint render_target_view_extent:9; + GLuint min_array_elt:11; GLuint min_lod:4; } ss4; + + struct { + GLuint pad1:16; + GLuint llc_mapping:1; + GLuint mlc_mapping:1; + GLuint gfdt:1; + GLuint gfdt_src:1; + GLuint y_offset:4; + GLuint pad0:1; + GLuint x_offset:7; + } ss5; /* NEW in Integrated Graphics Device */ + }; @@ -1302,6 +1396,17 @@ struct brw_instruction GLuint end_of_thread:1; } sampler; + struct { + GLuint binding_table_index:8; + GLuint sampler:4; + GLuint msg_type:4; + GLuint response_length:4; + GLuint msg_length:4; + GLuint msg_target:4; + GLuint pad1:3; + GLuint end_of_thread:1; + } sampler_igd; + struct brw_urb_immediate urb; struct { diff --git a/src/mesa/drivers/dri/i965/brw_urb.c b/src/mesa/drivers/dri/i965/brw_urb.c index 64f5904ac68..4ca6e99db0b 100644 --- a/src/mesa/drivers/dri/i965/brw_urb.c +++ b/src/mesa/drivers/dri/i965/brw_urb.c @@ -69,7 +69,7 @@ static GLboolean check_urb_layout( struct brw_context *brw ) brw->urb.sf_start = brw->urb.clip_start + brw->urb.nr_clip_entries * brw->urb.vsize; brw->urb.cs_start = brw->urb.sf_start + brw->urb.nr_sf_entries * brw->urb.sfsize; - return brw->urb.cs_start + brw->urb.nr_cs_entries * brw->urb.csize <= 256; + return brw->urb.cs_start + brw->urb.nr_cs_entries * brw->urb.csize <= URB_SIZES(brw); } /* Most minimal update, forces re-emit of URB fence packet after GS @@ -153,7 +153,7 @@ static void recalculate_urb_fence( struct brw_context *brw ) brw->urb.clip_start, brw->urb.sf_start, brw->urb.cs_start, - 256); + URB_SIZES(brw)); brw->state.dirty.brw |= BRW_NEW_URB_FENCE; } @@ -191,13 +191,13 @@ void brw_upload_urb_fence(struct brw_context *brw) /* The ordering below is correct, not the layout in the * instruction. * - * There are 256 urb reg pairs in total. + * There are 256/384 urb reg pairs in total. */ uf.bits0.vs_fence = brw->urb.gs_start; uf.bits0.gs_fence = brw->urb.clip_start; uf.bits0.clp_fence = brw->urb.sf_start; uf.bits1.sf_fence = brw->urb.cs_start; - uf.bits1.cs_fence = 256; + uf.bits1.cs_fence = URB_SIZES(brw); BRW_BATCH_STRUCT(brw, &uf); } diff --git a/src/mesa/drivers/dri/i965/brw_vs.c b/src/mesa/drivers/dri/i965/brw_vs.c index 038d7f7911c..656fa2e7834 100644 --- a/src/mesa/drivers/dri/i965/brw_vs.c +++ b/src/mesa/drivers/dri/i965/brw_vs.c @@ -49,7 +49,7 @@ static void do_vs_prog( struct brw_context *brw, memset(&c, 0, sizeof(c)); memcpy(&c.key, key, sizeof(*key)); - brw_init_compile(&c.func); + brw_init_compile(brw, &c.func); c.vp = vp; c.prog_data.outputs_written = vp->program.Base.OutputsWritten; diff --git a/src/mesa/drivers/dri/i965/brw_vs_emit.c b/src/mesa/drivers/dri/i965/brw_vs_emit.c index 447e1182b30..3cac97c71f4 100644 --- a/src/mesa/drivers/dri/i965/brw_vs_emit.c +++ b/src/mesa/drivers/dri/i965/brw_vs_emit.c @@ -867,7 +867,7 @@ static void emit_vertex_write( struct brw_vs_compile *c) * Later, clipping will detect ucp[6] and ensure the primitive is * clipped against all fixed planes. */ - if (!c->key.know_w_is_one) { + if (!BRW_IS_IGD(p->brw) && !c->key.know_w_is_one) { brw_CMP(p, vec8(brw_null_reg()), BRW_CONDITIONAL_L, diff --git a/src/mesa/drivers/dri/i965/brw_wm.c b/src/mesa/drivers/dri/i965/brw_wm.c index 2775fad37bd..dec91034c8d 100644 --- a/src/mesa/drivers/dri/i965/brw_wm.c +++ b/src/mesa/drivers/dri/i965/brw_wm.c @@ -155,7 +155,7 @@ static void do_wm_prog( struct brw_context *brw, c->env_param = brw->intel.ctx.FragmentProgram.Parameters; if (brw_wm_is_glsl(&c->fp->program)) { - brw_wm_glsl_emit(c); + brw_wm_glsl_emit(brw, c); } else { /* Augment fragment program. Add instructions for pre- and * post-fragment-program tasks such as interpolation and fogging. @@ -181,7 +181,7 @@ static void do_wm_prog( struct brw_context *brw, /* This is where we start emitting gen4 code: */ - brw_init_compile(&c->func); + brw_init_compile(brw, &c->func); brw_wm_pass2(c); diff --git a/src/mesa/drivers/dri/i965/brw_wm.h b/src/mesa/drivers/dri/i965/brw_wm.h index d4eb2330b7a..01e38598cfc 100644 --- a/src/mesa/drivers/dri/i965/brw_wm.h +++ b/src/mesa/drivers/dri/i965/brw_wm.h @@ -270,5 +270,5 @@ void brw_wm_lookup_iz( GLuint line_aa, struct brw_wm_prog_key *key ); GLboolean brw_wm_is_glsl(const struct gl_fragment_program *fp); -void brw_wm_glsl_emit(struct brw_wm_compile *c); +void brw_wm_glsl_emit(struct brw_context *brw, struct brw_wm_compile *c); #endif diff --git a/src/mesa/drivers/dri/i965/brw_wm_glsl.c b/src/mesa/drivers/dri/i965/brw_wm_glsl.c index 1ca5c67a0b0..0a93d06081c 100644 --- a/src/mesa/drivers/dri/i965/brw_wm_glsl.c +++ b/src/mesa/drivers/dri/i965/brw_wm_glsl.c @@ -1122,7 +1122,7 @@ static void post_wm_emit( struct brw_wm_compile *c ) } } -static void brw_wm_emit_glsl(struct brw_wm_compile *c) +static void brw_wm_emit_glsl(struct brw_context *brw, struct brw_wm_compile *c) { #define MAX_IFSN 32 @@ -1133,7 +1133,7 @@ static void brw_wm_emit_glsl(struct brw_wm_compile *c) struct brw_compile *p = &c->func; struct brw_indirect stack_index = brw_indirect(0, 0); - brw_init_compile(&c->func); + brw_init_compile(brw, &c->func); c->reg_index = 0; prealloc_reg(c); brw_set_compression_control(p, BRW_COMPRESSION_NONE); @@ -1358,11 +1358,11 @@ static void brw_wm_emit_glsl(struct brw_wm_compile *c) c->fp->program.Base.Instructions[i].Data = NULL; } -void brw_wm_glsl_emit(struct brw_wm_compile *c) +void brw_wm_glsl_emit(struct brw_context *brw, struct brw_wm_compile *c) { brw_wm_pass_fp(c); c->tmp_index = 127; - brw_wm_emit_glsl(c); + brw_wm_emit_glsl(brw, c); c->prog_data.total_grf = c->reg_index; c->prog_data.total_scratch = 0; } diff --git a/src/mesa/drivers/dri/i965/intel_context.c b/src/mesa/drivers/dri/i965/intel_context.c index 68b8bc14271..646e43eecf6 100644 --- a/src/mesa/drivers/dri/i965/intel_context.c +++ b/src/mesa/drivers/dri/i965/intel_context.c @@ -136,6 +136,9 @@ static const GLubyte *intelGetString( GLcontext *ctx, GLenum name ) case PCI_CHIP_I965_GME: chipset = "Intel(R) 965GME/GLE"; break; + case PCI_CHIP_IGD_GM: + chipset = "Intel(R) Integrated Graphics Device"; + break; default: chipset = "Unknown Intel Chipset"; } diff --git a/src/mesa/drivers/dri/intel/intel_chipset.h b/src/mesa/drivers/dri/intel/intel_chipset.h index 4fc4c963765..5f094dc5fb4 100644 --- a/src/mesa/drivers/dri/intel/intel_chipset.h +++ b/src/mesa/drivers/dri/intel/intel_chipset.h @@ -52,19 +52,25 @@ #define PCI_CHIP_I965_GM 0x2A02 #define PCI_CHIP_I965_GME 0x2A12 +#define PCI_CHIP_IGD_GM 0x2A42 + #define IS_MOBILE(devid) (devid == PCI_CHIP_I855_GM || \ devid == PCI_CHIP_I915_GM || \ devid == PCI_CHIP_I945_GM || \ devid == PCI_CHIP_I945_GME || \ devid == PCI_CHIP_I965_GM || \ - devid == PCI_CHIP_I965_GME) + devid == PCI_CHIP_I965_GME || \ + devid == PCI_CHIP_IGD_GM) + +#define IS_IGD(devid) (devid == PCI_CHIP_IGD_GM) #define IS_965(devid) (devid == PCI_CHIP_I965_G || \ devid == PCI_CHIP_I965_Q || \ devid == PCI_CHIP_I965_G_1 || \ devid == PCI_CHIP_I965_GM || \ devid == PCI_CHIP_I965_GME || \ - devid == PCI_CHIP_I946_GZ) + devid == PCI_CHIP_I946_GZ || \ + IS_IGD(devid)) #define IS_9XX(devid) (devid == PCI_CHIP_I915_G || \ devid == PCI_CHIP_I915_GM || \ diff --git a/src/mesa/drivers/dri/intel/intel_decode.c b/src/mesa/drivers/dri/intel/intel_decode.c index 73f0fcd5915..a1240639f4e 100644 --- a/src/mesa/drivers/dri/intel/intel_decode.c +++ b/src/mesa/drivers/dri/intel/intel_decode.c @@ -112,7 +112,7 @@ decode_mi(uint32_t *data, int count, uint32_t hw_offset, int *failures) for (opcode = 0; opcode < sizeof(opcodes_mi) / sizeof(opcodes_mi[0]); opcode++) { - if ((data[0] & 0x1e000000) >> 23 == opcodes_mi[opcode].opcode) { + if ((data[0] & 0x1f800000) >> 23 == opcodes_mi[opcode].opcode) { unsigned int len = 1, i; instr_out(data, hw_offset, 0, "%s\n", opcodes_mi[opcode].name); @@ -827,6 +827,8 @@ decode_3d_965(uint32_t *data, int count, uint32_t hw_offset, int *failures) { 0x6101, 6, 6, "STATE_BASE_ADDRESS" }, { 0x6102, 2, 2 , "STATE_SIP" }, { 0x6104, 1, 1, "3DSTATE_PIPELINE_SELECT" }, + { 0x680b, 1, 1, "3DSTATE_VF_STATISTICS" }, + { 0x6904, 1, 1, "3DSTATE_PIPELINE_SELECT" }, { 0x7800, 7, 7, "3DSTATE_PIPELINED_POINTERS" }, { 0x7801, 6, 6, "3DSTATE_BINDING_TABLE_POINTERS" }, { 0x780b, 1, 1, "3DSTATE_VF_STATISTICS" }, @@ -836,11 +838,12 @@ decode_3d_965(uint32_t *data, int count, uint32_t hw_offset, int *failures) /* 0x7809: 3DSTATE_VERTEX_ELEMENTS */ { 0x7900, 4, 4, "3DSTATE_DRAWING_RECTANGLE" }, { 0x7901, 5, 5, "3DSTATE_CONSTANT_COLOR" }, - { 0x7905, 5, 5, "3DSTATE_DEPTH_BUFFER" }, + { 0x7905, 5, 7, "3DSTATE_DEPTH_BUFFER" }, { 0x7906, 2, 2, "3DSTATE_POLY_STIPPLE_OFFSET" }, { 0x7907, 33, 33, "3DSTATE_POLY_STIPPLE_PATTERN" }, - { 0x7909, 2, 2, "3DSTATE_GLOBAL_DEPTH_OFFSET_CLAMP" }, { 0x7908, 3, 3, "3DSTATE_LINE_STIPPLE" }, + { 0x7909, 2, 2, "3DSTATE_GLOBAL_DEPTH_OFFSET_CLAMP" }, + { 0x790a, 3, 3, "3DSTATE_AA_LINE_PARAMETERS" }, { 0x7b00, 6, 6, "3DPRIMITIVE" }, };