From: Sebastien Bourdeauducq <sb@m-labs.hk>
Date: Tue, 3 Mar 2015 00:54:30 +0000 (+0000)
Subject: spiflash: style
X-Git-Tag: 24jan2021_ls180~2522
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=8e48502d0362bb71635d48daae7872a4ffbe076c;p=litex.git

spiflash: style
---

diff --git a/misoclib/mem/flash/spiflash/__init__.py b/misoclib/mem/flash/spiflash/__init__.py
index 090e818d..0d8cc890 100644
--- a/misoclib/mem/flash/spiflash/__init__.py
+++ b/misoclib/mem/flash/spiflash/__init__.py
@@ -30,7 +30,7 @@ class SpiFlash(Module, AutoCSR):
 
 		Supports multi-bit pseudo-parallel reads (aka Dual or Quad I/O Fast
 		Read). Only supports mode0 (cpol=0, cpha=0).
-		Optional supports software bitbanging (for write, erase, or other commands).
+		Optionally supports software bitbanging (for write, erase, or other commands).
 		"""
 		self.bus = bus = wishbone.Interface()
 		spi_width = flen(pads.dq)
@@ -39,7 +39,7 @@ class SpiFlash(Module, AutoCSR):
 			self.miso = CSRStatus()
 			self.bitbang_en = CSRStorage()
 
-		##
+		###
 
 		cs_n = Signal(reset=1)
 		clk = Signal()