From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Mon, 20 Jun 2022 15:58:21 +0000 (+0100)
Subject: cleanup sof and sif
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=8e49d0ecb3a0b38672e4cabaf6a7ef1fb5b3225b;p=libreriscv.git

cleanup sof and sif
---

diff --git a/openpower/sv/sif.py b/openpower/sv/sif.py
index adaf0b17d..46f6b4504 100644
--- a/openpower/sv/sif.py
+++ b/openpower/sv/sif.py
@@ -10,9 +10,9 @@ def sif(RA, mask=None, zero=False):
         if setting_mode and mask is not None and not (mask & bit):
             setting_mode = False # masked out, stop setting
         if setting_mode:
+            RT |= bit    # inclusively set bit in RT
             if RA & bit: # found a bit in rs1: stop setting RT
                 setting_mode = False
-            RT |= bit
         i += 1
     return RT
 
diff --git a/openpower/sv/sof.py b/openpower/sv/sof.py
index 164c32623..66f4b86af 100644
--- a/openpower/sv/sof.py
+++ b/openpower/sv/sof.py
@@ -8,14 +8,13 @@ def sof(RA, mask=None, zero=False):
         bit = 1<<i
         if not setting_mode and mask is not None and (mask & bit):
             setting_mode = True # back into "setting" mode
-            found = False
+            found = False       # start finding first
         if setting_mode:
             if mask is not None and not (mask & bit):
                 setting_mode = False
-            elif RA & bit: # found a bit in rs1: stop setting RT
-                if not found:
-                    found = True
-                    RT |= bit
+            elif RA & bit and not found: # found a bit: set if not found
+                RT |= bit
+                found = True # don't set another bit
         i += 1
     return RT