From: lkcl <lkcl@web>
Date: Wed, 27 Jul 2022 12:16:44 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: opf_rfc_ls005_v1~1014
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=8e4a623268d3319a9788064a4a4d7d37ca6898fd;p=libreriscv.git

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+# NL.net proposal
+
+
+## Project name
+
+OpenPOWER ISA RFCs
+
+## Website / wiki 
+
+<https://libre-soc.org/nlnet_2022_opf_isa_wg>
+
+Please be short and to the point in your answers; focus primarily on
+the what and how, not so much on the why. Add longer descriptions as
+attachments (see below). If English isn't your first language, don't
+worry - our reviewers don't care about spelling errors, only about
+great ideas. We apologise for the inconvenience of having to submit in
+English. On the up side, you can be as technical as you need to be (but
+you don't have to). Do stay concrete. Use plain text in your reply only,
+if you need any HTML to make your point please include this as attachment.
+
+## Abstract: Can you explain the whole project and its expected outcome(s).
+
+
+# Have you been involved with projects or organisations relevant to this project before? And if so, can you tell us a bit about your contributions?
+
+
+# Requested Amount    
+
+EUR 100,000.
+
+# Explain what the requested budget will be used for? 
+
+* Design and fabrication of Libre/Open Hardware Dual FPGA Carrier
+  boards (most likely accepting OrangeCrab as a module)
+* Porting of both LibreBMC and OpenBMC to the FPGA Board
+* Implementation of *server* side LPC (client-side already exists)
+* Verilator simulation of both client and server side LPC
+  and testing of the two simulations back-to-back
+
+# Compare your own project with existing or historical efforts.
+
+
+## What are significant technical challenges you expect to solve during the project, if any?
+
+
+
+## Describe the ecosystem of the project, and how you will engage with relevant actors and promote the outcomes?
+
+
+# Extra info to be submitted
+
+* TODO URLs etc