From: lkcl <lkcl@web>
Date: Sat, 11 Dec 2021 21:17:51 +0000 (+0000)
Subject: (no commit message)
X-Git-Tag: opf_rfc_ls005_v1~3286
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=8e673ca10e3cbdb2d3cfef16aca129a1066b97ed;p=libreriscv.git

---

diff --git a/openpower/sv/bitmanip.mdwn b/openpower/sv/bitmanip.mdwn
index 4f9abad97..63db85117 100644
--- a/openpower/sv/bitmanip.mdwn
+++ b/openpower/sv/bitmanip.mdwn
@@ -223,6 +223,17 @@ another mode selection would be CRs not Ints.
               crregs[BC][i]
         crregs[BA][i] = (imm & (1<<idx)) != 0
 
+## cmix
+
+based on RV bitmanip, covered by ternlog bitops
+
+```
+uint_xlen_t cmix(uint_xlen_t RA, uint_xlen_t RB, uint_xlen_t RC) {
+    return (RA & RB) | (RC & ~RB);
+}
+```
+
+
 # bitmask set
 
 based on RV bitmanip singlebit set, instruction format similar to shift
@@ -451,16 +462,6 @@ uint64_t gorc64(uint64_t RA, uint64_t RB)
 
 ```
 
-# cmix
-
-based on RV bitmanip, covered by ternlog bitops
-
-```
-uint_xlen_t cmix(uint_xlen_t RA, uint_xlen_t RB, uint_xlen_t RC) {
-    return (RA & RB) | (RC & ~RB);
-}
-```
-
 # carryless mul
 
 based on RV bitmanip