From: Florent Kermarrec Date: Sat, 28 Feb 2015 10:08:17 +0000 (+0100) Subject: liteeth: fix example design generation and remove VivadoProgrammer from platfom.... X-Git-Tag: 24jan2021_ls180~2569 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=8e67d6e69fb1d8152964ffad974444e9e70f9089;p=litex.git liteeth: fix example design generation and remove VivadoProgrammer from platfom. (TODO: remove others duplicates) --- diff --git a/misoclib/mem/litesata/core/link/crc.py b/misoclib/mem/litesata/core/link/crc.py index 7cb6e714..c33e715a 100644 --- a/misoclib/mem/litesata/core/link/crc.py +++ b/misoclib/mem/litesata/core/link/crc.py @@ -1,8 +1,6 @@ from collections import OrderedDict from misoclib.mem.litesata.common import * -from migen.actorlib.crc import CRCInserter, CRCChecker - class CRCEngine(Module): """Cyclic Redundancy Check Engine @@ -107,6 +105,163 @@ class LiteSATACRC(Module): self.error.eq(engine.next != self.check) ] + +class CRCInserter(Module): + """CRC Inserter + + Append a CRC at the end of each packet. + + Parameters + ---------- + layout : layout + Layout of the dataflow. + + Attributes + ---------- + sink : in + Packets input without CRC. + source : out + Packets output with CRC. + """ + def __init__(self, crc_class, layout): + self.sink = sink = Sink(layout) + self.source = source = Source(layout) + self.busy = Signal() + + ### + + dw = flen(sink.d) + crc = crc_class(dw) + fsm = FSM(reset_state="IDLE") + self.submodules += crc, fsm + + fsm.act("IDLE", + crc.reset.eq(1), + sink.ack.eq(1), + If(sink.stb & sink.sop, + sink.ack.eq(0), + NextState("COPY"), + ) + ) + fsm.act("COPY", + crc.ce.eq(sink.stb & source.ack), + crc.d.eq(sink.d), + Record.connect(sink, source), + source.eop.eq(0), + If(sink.stb & sink.eop & source.ack, + NextState("INSERT"), + ) + ) + ratio = crc.width//dw + if ratio > 1: + cnt = Signal(max=ratio, reset=ratio-1) + cnt_done = Signal() + fsm.act("INSERT", + source.stb.eq(1), + chooser(crc.value, cnt, source.d, reverse=True), + If(cnt_done, + source.eop.eq(1), + If(source.ack, NextState("IDLE")) + ) + ) + self.comb += cnt_done.eq(cnt == 0) + self.sync += \ + If(fsm.ongoing("IDLE"), + cnt.eq(cnt.reset) + ).Elif(fsm.ongoing("INSERT") & ~cnt_done, + cnt.eq(cnt - source.ack) + ) + else: + fsm.act("INSERT", + source.stb.eq(1), + source.eop.eq(1), + source.d.eq(crc.value), + If(source.ack, NextState("IDLE")) + ) + self.comb += self.busy.eq(~fsm.ongoing("IDLE")) + +class CRCChecker(Module): + """CRC Checker + + Check CRC at the end of each packet. + + Parameters + ---------- + layout : layout + Layout of the dataflow. + + Attributes + ---------- + sink : in + Packets input with CRC. + source : out + Packets output without CRC and "error" set to 0 + on eop when CRC OK / set to 1 when CRC KO. + """ + def __init__(self, crc_class, layout): + self.sink = sink = Sink(layout) + self.source = source = Source(layout) + self.busy = Signal() + + ### + + dw = flen(sink.d) + crc = crc_class(dw) + self.submodules += crc + ratio = crc.width//dw + + error = Signal() + fifo = InsertReset(SyncFIFO(layout, ratio + 1)) + self.submodules += fifo + + fsm = FSM(reset_state="RESET") + self.submodules += fsm + + fifo_in = Signal() + fifo_out = Signal() + fifo_full = Signal() + + self.comb += [ + fifo_full.eq(fifo.fifo.level == ratio), + fifo_in.eq(sink.stb & (~fifo_full | fifo_out)), + fifo_out.eq(source.stb & source.ack), + + Record.connect(sink, fifo.sink), + fifo.sink.stb.eq(fifo_in), + self.sink.ack.eq(fifo_in), + + source.stb.eq(sink.stb & fifo_full), + source.sop.eq(fifo.source.sop), + source.eop.eq(sink.eop), + fifo.source.ack.eq(fifo_out), + source.payload.eq(fifo.source.payload), + + source.error.eq(sink.error | crc.error), + ] + + fsm.act("RESET", + crc.reset.eq(1), + fifo.reset.eq(1), + NextState("IDLE"), + ) + fsm.act("IDLE", + crc.d.eq(sink.d), + If(sink.stb & sink.sop & sink.ack, + crc.ce.eq(1), + NextState("COPY") + ) + ) + fsm.act("COPY", + crc.d.eq(sink.d), + If(sink.stb & sink.ack, + crc.ce.eq(1), + If(sink.eop, + NextState("RESET") + ) + ) + ) + self.comb += self.busy.eq(~fsm.ongoing("IDLE")) + class LiteSATACRCInserter(CRCInserter): def __init__(self, description): CRCInserter.__init__(self, LiteSATACRC, description) diff --git a/misoclib/mem/litesata/example_designs/platforms/kc705.py b/misoclib/mem/litesata/example_designs/platforms/kc705.py index 43bc3e5a..17264498 100644 --- a/misoclib/mem/litesata/example_designs/platforms/kc705.py +++ b/misoclib/mem/litesata/example_designs/platforms/kc705.py @@ -1,35 +1,9 @@ from mibuild.generic_platform import * from mibuild.crg import SimpleCRG -from mibuild.xilinx_common import CRG_DS -from mibuild.xilinx_ise import XilinxISEPlatform -from mibuild.xilinx_vivado import XilinxVivadoPlatform -from mibuild.programmer import * - -def _run_vivado(cmds): - with subprocess.Popen("vivado -mode tcl", stdin=subprocess.PIPE, shell=True) as process: - process.stdin.write(cmds.encode("ASCII")) - process.communicate() - -class VivadoProgrammer(Programmer): - needs_bitreverse = False - - def load_bitstream(self, bitstream_file): - cmds = """open_hw -connect_hw_server -open_hw_target [lindex [get_hw_targets -of_objects [get_hw_servers localhost]] 0] - -set_property PROBES.FILE {{}} [lindex [get_hw_devices] 0] -set_property PROGRAM.FILE {{{bitstream}}} [lindex [get_hw_devices] 0] - -program_hw_devices [lindex [get_hw_devices] 0] -refresh_hw_device [lindex [get_hw_devices] 0] - -quit -""".format(bitstream=bitstream_file) - _run_vivado(cmds) - - def flash(self, address, data_file): - raise NotImplementedError +from mibuild.xilinx.common import CRG_DS +from mibuild.xilinx.ise import XilinxISEPlatform +from mibuild.xilinx.vivado import XilinxVivadoPlatform +from mibuild.xilinx.programmer import * _io = [ ("user_led", 0, Pins("AB8"), IOStandard("LVCMOS15")),