From: Gabe Black <gblack@eecs.umich.edu>
Date: Mon, 10 Sep 2007 18:01:52 +0000 (-0700)
Subject: X86: Move a comment to be next to the code it describes.
X-Git-Tag: m5_2.0_beta4~114
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=8e7bca8b360f973d1c0c8d5e0820a031144ff457;p=gem5.git

X86: Move a comment to be next to the code it describes.

--HG--
extra : convert_revision : c384391175babb7cfdd3885ae9d9f1a9405ea44f
---

diff --git a/src/arch/x86/isa/microops/regop.isa b/src/arch/x86/isa/microops/regop.isa
index 7ce9dc27f..d2cfff9d4 100644
--- a/src/arch/x86/isa/microops/regop.isa
+++ b/src/arch/x86/isa/microops/regop.isa
@@ -460,6 +460,11 @@ let {{
     class Xor(LogicRegOp):
         code = 'DestReg = merge(DestReg, psrc1 ^ op2, dataSize)'
 
+    # Neither of these is quite correct because it assumes that right shifting
+    # a signed or unsigned value does sign or zero extension respectively.
+    # The C standard says that what happens on a right shift with a 1 in the
+    # MSB position is undefined. On x86 and under likely most compilers the
+    # "right thing" happens, but this isn't a guarantee.
     class Mul1s(WrRegOp):
         code = '''
             ProdLow = psrc1 * op2;
@@ -489,11 +494,6 @@ let {{
     class Mulel(RdRegOp):
         code = 'DestReg = merge(SrcReg1, ProdLow, dataSize);'
 
-    # Neither of these is quite correct because it assumes that right shifting
-    # a signed or unsigned value does sign or zero extension respectively.
-    # The C standard says that what happens on a right shift with a 1 in the
-    # MSB position is undefined. On x86 and under likely most compilers the
-    # "right thing" happens, but this isn't a guarantee.
     class Muleh(RdRegOp):
         def __init__(self, dest, src1=None, flags=None, dataSize="env.dataSize"):
             if not src1: