From: Iago Toral Quiroga Date: Thu, 15 Sep 2016 08:49:40 +0000 (+0200) Subject: i965/vec4/tes: consider register offsets during attribute setup X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=8e92b402030735edab6c35e69dceee4acebb973b;p=mesa.git i965/vec4/tes: consider register offsets during attribute setup Reviewed-by: Matt Turner --- diff --git a/src/mesa/drivers/dri/i965/brw_vec4_tes.cpp b/src/mesa/drivers/dri/i965/brw_vec4_tes.cpp index bb81ad3a155..ae6d99bed83 100644 --- a/src/mesa/drivers/dri/i965/brw_vec4_tes.cpp +++ b/src/mesa/drivers/dri/i965/brw_vec4_tes.cpp @@ -84,8 +84,8 @@ vec4_tes_visitor::setup_payload() bool is_64bit = type_sz(inst->src[i].type) == 8; - struct brw_reg grf = - brw_vec4_grf(reg + inst->src[i].nr / 2, 4 * (inst->src[i].nr % 2)); + unsigned slot = inst->src[i].nr + inst->src[i].offset / 16; + struct brw_reg grf = brw_vec4_grf(reg + slot / 2, 4 * (slot % 2)); grf = stride(grf, 0, is_64bit ? 2 : 4, 1); grf.swizzle = inst->src[i].swizzle; grf.type = inst->src[i].type;