From: Clifford Wolf <clifford@clifford.at>
Date: Fri, 20 May 2016 15:13:11 +0000 (+0200)
Subject: Some fixes in tests/asicworld/*_tb.v
X-Git-Tag: yosys-0.7~215
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=8e9e793126a2772eed4b041bc60415943c71d5ee;p=yosys.git

Some fixes in tests/asicworld/*_tb.v
---

diff --git a/tests/asicworld/code_hdl_models_arbiter_tb.v b/tests/asicworld/code_hdl_models_arbiter_tb.v
index 5e7bf46b9..78d1168e6 100644
--- a/tests/asicworld/code_hdl_models_arbiter_tb.v
+++ b/tests/asicworld/code_hdl_models_arbiter_tb.v
@@ -1,11 +1,11 @@
 module testbench ();
 
-reg             clk;    
-reg             rst;    
-reg             req3;   
-reg             req2;   
-reg             req1;   
-reg             req0;   
+reg             clk = 0;
+reg             rst = 1;
+reg             req3 = 0;
+reg             req2 = 0;
+reg             req1 = 0;
+reg             req0 = 0;
 wire            gnt3;   
 wire            gnt2;   
 wire            gnt1;   
@@ -13,17 +13,15 @@ wire            gnt0;
 
 // Clock generator
 always #1 clk = ~clk;
+integer file;
+
+always @(posedge clk)
+  $fdisplay(file, "%b", {gnt3, gnt2, gnt1, gnt0});
 
 initial begin
-  $dumpfile ("arbiter.vcd");
-  $dumpvars();
-  clk = 0;
-  rst = 1;
-  req0 = 0;
-  req1 = 0;
-  req2 = 0;
-  req3 = 0;
-  #10 rst = 0;
+  file = $fopen(`outfile);
+  repeat (5) @ (posedge clk);
+  rst <= 0;
   repeat (1) @ (posedge clk);
   req0 <= 1;
   repeat (1) @ (posedge clk);
diff --git a/tests/asicworld/code_verilog_tutorial_counter_tb.v b/tests/asicworld/code_verilog_tutorial_counter_tb.v
index 504814543..33d540509 100644
--- a/tests/asicworld/code_verilog_tutorial_counter_tb.v
+++ b/tests/asicworld/code_verilog_tutorial_counter_tb.v
@@ -15,9 +15,10 @@
 ///////////////////////////////////////////////////////////////////////////
 module testbench;
 
-reg clk, reset, enable;
+integer file;
+reg clk = 0, reset = 0, enable = 0;
 wire [3:0] count;
-reg dut_error;
+reg dut_error = 0;
 
 counter U0 (
 .clk    (clk),
@@ -30,34 +31,21 @@ event reset_enable;
 event terminate_sim;
 
 initial
-begin
- $display ("###################################################");
- clk = 0;
- reset = 0;
- enable = 0;
- dut_error = 0;
-end
+ file = $fopen(`outfile);
 
 always
   #5 clk = !clk;
 
-initial
-begin
-  $dumpfile ("counter.vcd");
-  $dumpvars;
-end
-
-
 initial
 @ (terminate_sim)  begin
- $display ("Terminating simulation");
+ $fdisplay (file, "Terminating simulation");
  if (dut_error == 0) begin
-   $display ("Simulation Result : PASSED");
+   $fdisplay (file, "Simulation Result : PASSED");
  end
  else begin
-   $display ("Simulation Result : FAILED");
+   $fdisplay (file, "Simulation Result : FAILED");
  end
- $display ("###################################################");
+ $fdisplay (file, "###################################################");
  #1 $finish;
 end
 
@@ -69,11 +57,11 @@ initial
 forever begin
  @ (reset_enable);
  @ (negedge clk)
- $display ("Applying reset");
+ $fdisplay (file, "Applying reset");
    reset = 1;
  @ (negedge clk)
    reset = 0;
- $display ("Came out of Reset");
+ $fdisplay (file, "Came out of Reset");
  -> reset_done;
 end
 
@@ -103,8 +91,8 @@ else if ( enable == 1'b1)
 
 always @ (negedge clk)
 if (count_compare != count) begin
-  $display ("DUT ERROR AT TIME%d",$time);
-  $display ("Expected value %d, Got Value %d", count_compare, count);
+  $fdisplay (file, "DUT ERROR AT TIME%d",$time);
+  $fdisplay (file, "Expected value %d, Got Value %d", count_compare, count);
   dut_error = 1;
   #5 -> terminate_sim;
 end
diff --git a/tests/asicworld/code_verilog_tutorial_first_counter_tb.v b/tests/asicworld/code_verilog_tutorial_first_counter_tb.v
index f065732be..806e17736 100644
--- a/tests/asicworld/code_verilog_tutorial_first_counter_tb.v
+++ b/tests/asicworld/code_verilog_tutorial_first_counter_tb.v
@@ -1,16 +1,13 @@
 module testbench();
 // Declare inputs as regs and outputs as wires
-reg clock, reset, enable;
+reg clock = 1, reset = 0, enable = 0;
 wire [3:0] counter_out;
+integer file;
 
 // Initialize all variables
 initial begin        
-  $display ("time\t clk reset enable counter");	
-  $monitor ("%g\t %b   %b     %b      %b", 
-	  $time, clock, reset, enable, counter_out);	
-  clock = 1;       // initial value of clock
-  reset = 0;       // initial value of reset
-  enable = 0;      // initial value of enable
+  file = $fopen(`outfile);
+  $fdisplay (file, "time\t clk reset enable counter");	
   #5 reset = 1;    // Assert the reset
   #10 reset = 0;   // De-assert the reset
   #10 enable = 1;  // Assert enable
@@ -18,6 +15,10 @@ initial begin
   #5 $finish;      // Terminate simulation
 end
 
+always @(negedge clock)
+  $fdisplay (file, "%g\t %b   %b     %b      %b", 
+	  $time, clock, reset, enable, counter_out);	
+
 // Clock generator
 initial begin
   #1;
diff --git a/tests/asicworld/code_verilog_tutorial_fsm_full_tb.v b/tests/asicworld/code_verilog_tutorial_fsm_full_tb.v
index 2e9448950..a8e15568b 100644
--- a/tests/asicworld/code_verilog_tutorial_fsm_full_tb.v
+++ b/tests/asicworld/code_verilog_tutorial_fsm_full_tb.v
@@ -1,14 +1,14 @@
 module testbench();
-reg clock , reset ;
+reg clock = 0 , reset ;
 reg req_0 , req_1 ,  req_2 , req_3; 
 wire gnt_0 , gnt_1 , gnt_2 , gnt_3 ;
+integer file;
 
 initial begin
   // $dumpfile("testbench.vcd");
   // $dumpvars(0, testbench);
-  $display("Time\t    R0 R1 R2 R3 G0 G1 G2 G3");
-  $monitor("%g\t    %b  %b  %b  %b  %b  %b  %b  %b", 
-    $time, req_0, req_1, req_2, req_3, gnt_0, gnt_1, gnt_2, gnt_3);
+  file = $fopen(`outfile);
+  $fdisplay(file, "Time\t    R0 R1 R2 R3 G0 G1 G2 G3");
   clock = 0;
   reset = 1;
   req_0 = 0;
@@ -28,6 +28,10 @@ initial begin
   #10 $finish;
 end
 
+always @(negedge clock)
+  $fdisplay(file, "%g\t    %b  %b  %b  %b  %b  %b  %b  %b", 
+    $time, req_0, req_1, req_2, req_3, gnt_0, gnt_1, gnt_2, gnt_3);
+
 initial begin
  #1;
  forever