From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sun, 24 May 2020 22:00:59 +0000 (+0100)
Subject: add comments for SPR pipe_data
X-Git-Tag: div_pipeline~859
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=8ea22ecbaea42108638ed514f45346f92592b22b;p=soc.git

add comments for SPR pipe_data
---

diff --git a/src/soc/fu/spr/pipe_data.py b/src/soc/fu/spr/pipe_data.py
index 717dff2a..6871aa98 100644
--- a/src/soc/fu/spr/pipe_data.py
+++ b/src/soc/fu/spr/pipe_data.py
@@ -1,3 +1,14 @@
+"""SPR Pipeline Data structures
+
+Covers MFSPR and MTSPR.  however given that the SPRs are split across
+XER (which is 3 separate registers), Fast-SPR and Slow-SPR regfiles,
+the data structures are slightly more involved than just "INT, SPR".
+
+Links:
+* https://bugs.libre-soc.org/show_bug.cgi?id=348
+* https://libre-soc.org/openpower/isa/sprset/
+"""
+
 from nmigen import Signal, Const
 from ieee754.fpcommon.getop import FPPipeContext
 from soc.fu.pipe_data import IntegerData