From: Michael Nolan <mtnolan2640@gmail.com>
Date: Thu, 7 May 2020 14:37:20 +0000 (-0400)
Subject: Add test_mfcr
X-Git-Tag: div_pipeline~1361
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=8ea804463351bc17032f450beadf3f20d42af84b;p=soc.git

Add test_mfcr
---

diff --git a/src/soc/decoder/isa/test_caller.py b/src/soc/decoder/isa/test_caller.py
index 21364340..78766f6c 100644
--- a/src/soc/decoder/isa/test_caller.py
+++ b/src/soc/decoder/isa/test_caller.py
@@ -128,8 +128,11 @@ class DecoderTestCase(FHDLTestCase):
             self.assertEqual(sim.gpr(1), SelectableInt(0x1234, 64))
             self.assertEqual(sim.gpr(2), SelectableInt(0, 64))
 
-
-
+    def test_mfcr(self):
+        lst = ["mfcr 1"]
+        with Program(lst) as program:
+            sim = self.run_tst_program(program)
+            self.assertEqual(sim.gpr(1), SelectableInt(0, 64))
 
     def test_mtcrf(self):
         for i in range(4):
diff --git a/src/soc/decoder/selectable_int.py b/src/soc/decoder/selectable_int.py
index 33cbb74e..1227335e 100644
--- a/src/soc/decoder/selectable_int.py
+++ b/src/soc/decoder/selectable_int.py
@@ -342,6 +342,8 @@ def selectconcat(*args, repeat=1):
         args = tmp
     res = copy(args[0])
     for i in args[1:]:
+        if isinstance(i, FieldSelectableInt):
+            i = i.si
         assert isinstance(i, SelectableInt), "can only concat SIs, sorry"
         res.bits += i.bits
         res.value = (res.value << i.bits) | i.value