From: lkcl <lkcl@web>
Date: Sat, 23 Jul 2022 10:50:52 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: opf_rfc_ls005_v1~1095
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=8edb907bdedae335d0e61cb41f2b0bfb8561ffdc;p=libreriscv.git

---

diff --git a/openpower/sv/executive_summary.mdwn b/openpower/sv/executive_summary.mdwn
index 304f63a6c..657ad6a09 100644
--- a/openpower/sv/executive_summary.mdwn
+++ b/openpower/sv/executive_summary.mdwn
@@ -20,7 +20,7 @@ presents the programmer with explicit control over Vector length.
 ARM NEON, AVX-512 and ARM SVE2 are all Predicated SIMD ISAs and
 **do not provide Scalability to the Programmer** (SVE2 is **Silicon**
 Scalable, not **Programmer** Scalable: the distinction is profoundly
-critical).
+important).
 For Predicated SIMD, Programmers must emulate scaling
 through explicit predicate masking, which increases instruction count in
 hot-loops.