From: lkcl <lkcl@web>
Date: Fri, 17 Sep 2021 14:55:54 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: DRAFT_SVP64_0_1~88
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=8eedabed85a9266e6f93cc80efda8b2580b00cf9;p=libreriscv.git

---

diff --git a/openpower/sv/svp64/appendix.mdwn b/openpower/sv/svp64/appendix.mdwn
index 15bfb6b7a..068466df3 100644
--- a/openpower/sv/svp64/appendix.mdwn
+++ b/openpower/sv/svp64/appendix.mdwn
@@ -543,9 +543,12 @@ result of the operation as one part of that element *and a corresponding
 CR element*.  Greatly simplified pseudocode:
 
     for i in range(VL):
-         # calculate the vector result of an add iregs[RT+i] = iregs[RA+i]
-         + iregs[RB+i] # now calculate CR bits CRs{8+i}.eq = iregs[RT+i]
-         == 0 CRs{8+i}.gt = iregs[RT+i] > 0 ... etc
+         # calculate the vector result of an add
+         iregs[RT+i] = iregs[RA+i] + iregs[RB+i]
+         # now calculate CR bits
+         CRs{8+i}.eq = iregs[RT+i] == 0
+         CRs{8+i}.gt = iregs[RT+i] > 0
+         ... etc
 
 If a "cumulated" CR based analysis of results is desired (a la VSX CR6)
 then a followup instruction must be performed, setting "reduce" mode on