From: Kenneth Graunke Date: Wed, 14 May 2014 04:52:51 +0000 (-0700) Subject: i965/fs: Move payload register info from brw_wm_compile to fs_visitor. X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=8ef78828fadb0f35b07be93492b3d7c297bb9ffd;p=mesa.git i965/fs: Move payload register info from brw_wm_compile to fs_visitor. This data is created by fs_visitor and only used when emitting code, so keeping it in fs_visitor makes sense. I decided it would be reasonable to group these all together in a struct, since they're highly related. v2: s/nr_payload_regs/payload.num_regs/ in some comments (chrisf). Signed-off-by: Kenneth Graunke Reviewed-by: Chris Forbes --- diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp b/src/mesa/drivers/dri/i965/brw_fs.cpp index 336b8e608fc..10a9524ad17 100644 --- a/src/mesa/drivers/dri/i965/brw_fs.cpp +++ b/src/mesa/drivers/dri/i965/brw_fs.cpp @@ -1059,7 +1059,7 @@ fs_visitor::emit_fragcoord_interpolation(ir_variable *ir) /* gl_FragCoord.z */ if (brw->gen >= 6) { - emit(MOV(wpos, fs_reg(brw_vec8_grf(c->source_depth_reg, 0)))); + emit(MOV(wpos, fs_reg(brw_vec8_grf(payload.source_depth_reg, 0)))); } else { emit(FS_OPCODE_LINTERP, wpos, this->delta_x[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC], @@ -1260,7 +1260,7 @@ fs_visitor::emit_samplepos_setup(ir_variable *ir) * the positions using vstride=16, width=8, hstride=2. */ struct brw_reg sample_pos_reg = - stride(retype(brw_vec1_grf(c->sample_pos_reg, 0), + stride(retype(brw_vec1_grf(payload.sample_pos_reg, 0), BRW_REGISTER_TYPE_B), 16, 8, 2); emit(MOV(int_sample_x, fs_reg(sample_pos_reg))); @@ -1447,9 +1447,9 @@ void fs_visitor::assign_curb_setup() { if (dispatch_width == 8) { - c->prog_data.first_curbe_grf = c->nr_payload_regs; + c->prog_data.first_curbe_grf = payload.num_regs; } else { - c->prog_data.first_curbe_grf_16 = c->nr_payload_regs; + c->prog_data.first_curbe_grf_16 = payload.num_regs; } c->prog_data.curb_read_length = ALIGN(stage_prog_data->nr_params, 8) / 8; @@ -1473,7 +1473,7 @@ fs_visitor::assign_curb_setup() constant_nr = 0; } - struct brw_reg brw_reg = brw_vec1_grf(c->nr_payload_regs + + struct brw_reg brw_reg = brw_vec1_grf(payload.num_regs + constant_nr / 8, constant_nr % 8); @@ -1574,7 +1574,7 @@ fs_visitor::calculate_urb_setup() void fs_visitor::assign_urb_setup() { - int urb_start = c->nr_payload_regs + c->prog_data.curb_read_length; + int urb_start = payload.num_regs + c->prog_data.curb_read_length; /* Offset all the urb_setup[] index by the actual position of the * setup regs, now that the location of the constants has been chosen. @@ -2802,7 +2802,7 @@ fs_visitor::setup_payload_gen6() assert(brw->gen >= 6); /* R0-1: masks, pixel X/Y coordinates. */ - c->nr_payload_regs = 2; + payload.num_regs = 2; /* R2: only for 32-pixel dispatch.*/ /* R3-26: barycentric interpolation coordinates. These appear in the @@ -2814,48 +2814,48 @@ fs_visitor::setup_payload_gen6() */ for (int i = 0; i < BRW_WM_BARYCENTRIC_INTERP_MODE_COUNT; ++i) { if (barycentric_interp_modes & (1 << i)) { - c->barycentric_coord_reg[i] = c->nr_payload_regs; - c->nr_payload_regs += 2; + payload.barycentric_coord_reg[i] = payload.num_regs; + payload.num_regs += 2; if (dispatch_width == 16) { - c->nr_payload_regs += 2; + payload.num_regs += 2; } } } /* R27: interpolated depth if uses source depth */ if (uses_depth) { - c->source_depth_reg = c->nr_payload_regs; - c->nr_payload_regs++; + payload.source_depth_reg = payload.num_regs; + payload.num_regs++; if (dispatch_width == 16) { /* R28: interpolated depth if not SIMD8. */ - c->nr_payload_regs++; + payload.num_regs++; } } /* R29: interpolated W set if GEN6_WM_USES_SOURCE_W. */ if (uses_depth) { - c->source_w_reg = c->nr_payload_regs; - c->nr_payload_regs++; + payload.source_w_reg = payload.num_regs; + payload.num_regs++; if (dispatch_width == 16) { /* R30: interpolated W if not SIMD8. */ - c->nr_payload_regs++; + payload.num_regs++; } } c->prog_data.uses_pos_offset = c->key.compute_pos_offset; /* R31: MSAA position offsets. */ if (c->prog_data.uses_pos_offset) { - c->sample_pos_reg = c->nr_payload_regs; - c->nr_payload_regs++; + payload.sample_pos_reg = payload.num_regs; + payload.num_regs++; } /* R32: MSAA input coverage mask */ if (fp->Base.SystemValuesRead & SYSTEM_BIT_SAMPLE_MASK_IN) { assert(brw->gen >= 7); - c->sample_mask_in_reg = c->nr_payload_regs; - c->nr_payload_regs++; + payload.sample_mask_in_reg = payload.num_regs; + payload.num_regs++; if (dispatch_width == 16) { /* R33: input coverage mask if not SIMD8. */ - c->nr_payload_regs++; + payload.num_regs++; } } diff --git a/src/mesa/drivers/dri/i965/brw_fs.h b/src/mesa/drivers/dri/i965/brw_fs.h index dac2d8ad36b..28118647905 100644 --- a/src/mesa/drivers/dri/i965/brw_fs.h +++ b/src/mesa/drivers/dri/i965/brw_fs.h @@ -552,6 +552,20 @@ public: /* Result of last visit() method. */ fs_reg result; + /** Register numbers for thread payload fields. */ + struct { + uint8_t source_depth_reg; + uint8_t source_w_reg; + uint8_t aa_dest_stencil_reg; + uint8_t dest_depth_reg; + uint8_t sample_pos_reg; + uint8_t sample_mask_in_reg; + uint8_t barycentric_coord_reg[BRW_WM_BARYCENTRIC_INTERP_MODE_COUNT]; + + /** The number of thread payload registers the hardware will supply. */ + uint8_t num_regs; + } payload; + fs_reg pixel_x; fs_reg pixel_y; fs_reg wpos_w; diff --git a/src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp b/src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp index f51f0b89e99..717a94e90f3 100644 --- a/src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp +++ b/src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp @@ -222,9 +222,9 @@ count_to_loop_end(fs_inst *do_inst) * * The layout of the payload registers is: * - * 0..nr_payload_regs-1: fixed function setup (including bary coordinates). - * nr_payload_regs..nr_payload_regs+curb_read_lengh-1: uniform data - * nr_payload_regs+curb_read_lengh..first_non_payload_grf-1: setup coefficients. + * 0..payload.num_regs-1: fixed function setup (including bary coordinates). + * payload.num_regs..payload.num_regs+curb_read_lengh-1: uniform data + * payload.num_regs+curb_read_lengh..first_non_payload_grf-1: setup coefficients. * * And we have payload_node_count nodes covering these registers in order * (note that in SIMD16, a node is two registers). diff --git a/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp b/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp index eff762975ae..64cf8aede21 100644 --- a/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp +++ b/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp @@ -139,8 +139,9 @@ fs_visitor::visit(ir_variable *ir) reg = emit_sampleid_setup(ir); } else if (ir->data.location == SYSTEM_VALUE_SAMPLE_MASK_IN) { assert(brw->gen >= 7); - reg = new(mem_ctx) fs_reg(retype(brw_vec8_grf(c->sample_mask_in_reg, 0), - BRW_REGISTER_TYPE_D)); + reg = new(mem_ctx) + fs_reg(retype(brw_vec8_grf(payload.sample_mask_in_reg, 0), + BRW_REGISTER_TYPE_D)); } } @@ -2588,12 +2589,12 @@ fs_visitor::emit_interpolation_setup_gen6() emit(MOV(this->pixel_y, int_pixel_y)); this->current_annotation = "compute pos.w"; - this->pixel_w = fs_reg(brw_vec8_grf(c->source_w_reg, 0)); + this->pixel_w = fs_reg(brw_vec8_grf(payload.source_w_reg, 0)); this->wpos_w = fs_reg(this, glsl_type::float_type); emit_math(SHADER_OPCODE_RCP, this->wpos_w, this->pixel_w); for (int i = 0; i < BRW_WM_BARYCENTRIC_INTERP_MODE_COUNT; ++i) { - uint8_t reg = c->barycentric_coord_reg[i]; + uint8_t reg = payload.barycentric_coord_reg[i]; this->delta_x[i] = fs_reg(brw_vec8_grf(reg, 0)); this->delta_y[i] = fs_reg(brw_vec8_grf(reg + 1, 0)); } @@ -2767,10 +2768,10 @@ fs_visitor::emit_fb_writes() nr += 2; } - if (c->aa_dest_stencil_reg) { + if (payload.aa_dest_stencil_reg) { push_force_uncompressed(); emit(MOV(fs_reg(MRF, nr++), - fs_reg(brw_vec8_grf(c->aa_dest_stencil_reg, 0)))); + fs_reg(brw_vec8_grf(payload.aa_dest_stencil_reg, 0)))); pop_force_uncompressed(); } @@ -2809,14 +2810,14 @@ fs_visitor::emit_fb_writes() } else { /* Pass through the payload depth. */ emit(MOV(fs_reg(MRF, nr), - fs_reg(brw_vec8_grf(c->source_depth_reg, 0)))); + fs_reg(brw_vec8_grf(payload.source_depth_reg, 0)))); } nr += reg_width; } - if (c->dest_depth_reg) { + if (payload.dest_depth_reg) { emit(MOV(fs_reg(MRF, nr), - fs_reg(brw_vec8_grf(c->dest_depth_reg, 0)))); + fs_reg(brw_vec8_grf(payload.dest_depth_reg, 0)))); nr += reg_width; } @@ -2971,6 +2972,7 @@ fs_visitor::fs_visitor(struct brw_context *brw, hash_table_pointer_hash, hash_table_pointer_compare); + memset(&this->payload, 0, sizeof(this->payload)); memset(this->outputs, 0, sizeof(this->outputs)); memset(this->output_components, 0, sizeof(this->output_components)); this->first_non_payload_grf = 0; diff --git a/src/mesa/drivers/dri/i965/brw_wm.h b/src/mesa/drivers/dri/i965/brw_wm.h index 8ab0b079c5f..b3f383d2cdc 100644 --- a/src/mesa/drivers/dri/i965/brw_wm.h +++ b/src/mesa/drivers/dri/i965/brw_wm.h @@ -84,14 +84,6 @@ struct brw_wm_compile { struct brw_wm_prog_key key; struct brw_wm_prog_data prog_data; - uint8_t source_depth_reg; - uint8_t source_w_reg; - uint8_t aa_dest_stencil_reg; - uint8_t dest_depth_reg; - uint8_t sample_pos_reg; - uint8_t sample_mask_in_reg; - uint8_t barycentric_coord_reg[BRW_WM_BARYCENTRIC_INTERP_MODE_COUNT]; - uint8_t nr_payload_regs; GLuint source_depth_to_render_target:1; GLuint runtime_check_aads_emit:1; }; diff --git a/src/mesa/drivers/dri/i965/brw_wm_iz.cpp b/src/mesa/drivers/dri/i965/brw_wm_iz.cpp index a91f6843fe2..f51802b860f 100644 --- a/src/mesa/drivers/dri/i965/brw_wm_iz.cpp +++ b/src/mesa/drivers/dri/i965/brw_wm_iz.cpp @@ -143,7 +143,7 @@ void fs_visitor::setup_payload_gen4() if (wm_iz_table[lookup].sd_present || uses_depth || kill_stats_promoted_workaround) { - c->source_depth_reg = reg; + payload.source_depth_reg = reg; reg += 2; } @@ -151,17 +151,17 @@ void fs_visitor::setup_payload_gen4() c->source_depth_to_render_target = 1; if (wm_iz_table[lookup].ds_present || c->key.line_aa != AA_NEVER) { - c->aa_dest_stencil_reg = reg; + payload.aa_dest_stencil_reg = reg; c->runtime_check_aads_emit = (!wm_iz_table[lookup].ds_present && c->key.line_aa == AA_SOMETIMES); reg++; } if (wm_iz_table[lookup].dd_present) { - c->dest_depth_reg = reg; + payload.dest_depth_reg = reg; reg+=2; } - c->nr_payload_regs = reg; + payload.num_regs = reg; }