From: Tuan Ta <qtt2@cornell.edu>
Date: Tue, 5 Feb 2019 15:08:10 +0000 (-0500)
Subject: arch-riscv: Initialize interrupt mask
X-Git-Tag: v19.0.0.0~1188
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=8efcc0faac252d716704b5f8f9f3e1c165910ebe;p=gem5.git

arch-riscv: Initialize interrupt mask

This patch initializes RISCV interrupt mask to 0.

Change-Id: I56289d9f3f319e239e305befea006a0ad4d86b75
Reviewed-on: https://gem5-review.googlesource.com/c/16162
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
---

diff --git a/src/arch/riscv/interrupts.hh b/src/arch/riscv/interrupts.hh
index 406fe4ffa..ed946879b 100644
--- a/src/arch/riscv/interrupts.hh
+++ b/src/arch/riscv/interrupts.hh
@@ -74,7 +74,7 @@ class Interrupts : public SimObject
     std::bitset<NumInterruptTypes>
     globalMask(ThreadContext *tc) const
     {
-        INTERRUPT mask;
+        INTERRUPT mask = 0;
         STATUS status = tc->readMiscReg(MISCREG_STATUS);
         if (status.mie)
             mask.mei = mask.mti = mask.msi = 1;