From: Jan Hubicka Date: Fri, 17 Oct 2003 03:32:21 +0000 (+0200) Subject: re PR rtl-optimization/12630 (Various unrecognizable insns and ICEs at -O3) X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=8f00386e581a1e56da39fd0ea34f4b32ce631a8e;p=gcc.git re PR rtl-optimization/12630 (Various unrecognizable insns and ICEs at -O3) PR optimization/12630 * pa.md (movstrsi, movstrsi_internal): Use match_scratch in clobbers for operands 7 and 8. From-SVN: r72590 --- diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 37050c108fe..640ad1a68a4 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,9 @@ +2003-10-16 Jan Hubicka + + PR optimization/12630 + * pa.md (movstrsi, movstrsi_internal): Use match_scratch in clobbers + for operands 7 and 8. + 2003-10-16 Kelley Cook * objc/Make-lang.in (objc-parse.o): Honor $(parsedir) for objc-parse.c. diff --git a/gcc/config/pa/pa.md b/gcc/config/pa/pa.md index f6d9238c691..958c635670d 100644 --- a/gcc/config/pa/pa.md +++ b/gcc/config/pa/pa.md @@ -2945,8 +2945,8 @@ (define_expand "movstrsi" [(parallel [(set (match_operand:BLK 0 "" "") (match_operand:BLK 1 "" "")) - (clobber (match_dup 7)) - (clobber (match_dup 8)) + (clobber (match_scratch:SI 7 "")) + (clobber (match_scratch:SI 8 "")) (clobber (match_dup 4)) (clobber (match_dup 5)) (clobber (match_dup 6)) @@ -3016,10 +3016,10 @@ ;; therefore it is forced to operand 2. If the count is compile-time ;; determined, we need two scratch registers for the unrolled code. (define_insn "movstrsi_internal" - [(set (mem:BLK (match_operand:SI 0 "register_operand" "+r,r")) - (mem:BLK (match_operand:SI 1 "register_operand" "+r,r"))) - (clobber (match_dup 0)) - (clobber (match_dup 1)) + [(set (mem:BLK (match_operand:SI 0 "register_operand" "r,r")) + (mem:BLK (match_operand:SI 1 "register_operand" "r,r"))) + (clobber (match_scratch:SI 7 "=0,0")) + (clobber (match_scratch:SI 8 "=1,1")) (clobber (match_operand:SI 2 "register_operand" "=r,r")) ;loop cnt/tmp (clobber (match_operand:SI 3 "register_operand" "=&r,&r")) ;item tmp (clobber (match_operand:SI 6 "register_operand" "=&r,&r")) ;item tmp2