From: Marcelina Kościelnicka <mwk@0x04.net>
Date: Tue, 23 Jun 2020 21:16:43 +0000 (+0200)
Subject: simplemap: Fix $dffsre mapping.
X-Git-Tag: working-ls180~452
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=8f12c5b063a458ac5f751f54651baebd84006307;p=yosys.git

simplemap: Fix $dffsre mapping.
---

diff --git a/passes/techmap/simplemap.cc b/passes/techmap/simplemap.cc
index c8388e2d7..b9d337da4 100644
--- a/passes/techmap/simplemap.cc
+++ b/passes/techmap/simplemap.cc
@@ -489,7 +489,7 @@ void simplemap_dffsre(RTLIL::Module *module, RTLIL::Cell *cell)
 	RTLIL::SigSpec sig_d = cell->getPort(ID::D);
 	RTLIL::SigSpec sig_q = cell->getPort(ID::Q);
 
-	IdString gate_type = stringf("$_DFFSR_%c%c%c%c_", clk_pol, set_pol, clr_pol, en_pol);
+	IdString gate_type = stringf("$_DFFSRE_%c%c%c%c_", clk_pol, set_pol, clr_pol, en_pol);
 
 	for (int i = 0; i < width; i++) {
 		RTLIL::Cell *gate = module->addCell(NEW_ID, gate_type);