From: Francisco Jerez Date: Fri, 13 Jan 2017 23:23:48 +0000 (-0800) Subject: intel/fs: Wrap FS payload register look-up in a helper function. X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=8f143f70d64786a521fe57f109bff9a084cdf27f;p=mesa.git intel/fs: Wrap FS payload register look-up in a helper function. Reviewed-by: Jason Ekstrand Reviewed-by: Matt Turner --- diff --git a/src/intel/compiler/brw_fs.cpp b/src/intel/compiler/brw_fs.cpp index 893a7e2e526..18bcdc4f8b3 100644 --- a/src/intel/compiler/brw_fs.cpp +++ b/src/intel/compiler/brw_fs.cpp @@ -1075,7 +1075,7 @@ fs_visitor::emit_fragcoord_interpolation(fs_reg wpos) /* gl_FragCoord.z */ if (devinfo->gen >= 6) { - bld.MOV(wpos, fs_reg(brw_vec8_grf(payload.source_depth_reg, 0))); + bld.MOV(wpos, fetch_payload_reg(bld, payload.source_depth_reg)); } else { bld.emit(FS_OPCODE_LINTERP, wpos, this->delta_xy[BRW_BARYCENTRIC_PERSPECTIVE_PIXEL], @@ -1213,8 +1213,8 @@ fs_visitor::emit_samplepos_setup() * The X, Y sample positions come in as bytes in thread payload. So, read * the positions using vstride=16, width=8, hstride=2. */ - const fs_reg sample_pos_reg = retype(brw_vec8_grf(payload.sample_pos_reg, 0), - BRW_REGISTER_TYPE_W); + const fs_reg sample_pos_reg = + fetch_payload_reg(abld, payload.sample_pos_reg, BRW_REGISTER_TYPE_W); /* Compute gl_SamplePosition.x */ abld.MOV(int_sample_x, subscript(sample_pos_reg, BRW_REGISTER_TYPE_B, 0)); @@ -1331,8 +1331,8 @@ fs_visitor::emit_samplemaskin_setup() fs_reg *reg = new(this->mem_ctx) fs_reg(vgrf(glsl_type::int_type)); - fs_reg coverage_mask(retype(brw_vec8_grf(payload.sample_mask_in_reg, 0), - BRW_REGISTER_TYPE_D)); + fs_reg coverage_mask = + fetch_payload_reg(bld, payload.sample_mask_in_reg, BRW_REGISTER_TYPE_D); if (wm_prog_data->persample_dispatch) { /* gl_SampleMaskIn[] comes from two sources: the input coverage mask, diff --git a/src/intel/compiler/brw_fs.h b/src/intel/compiler/brw_fs.h index 260e40ef37d..f0b2d5e8ad3 100644 --- a/src/intel/compiler/brw_fs.h +++ b/src/intel/compiler/brw_fs.h @@ -497,6 +497,19 @@ private: void *mem_ctx; }; +namespace brw { + inline fs_reg + fetch_payload_reg(const brw::fs_builder &bld, uint8_t reg, + brw_reg_type type = BRW_REGISTER_TYPE_F, unsigned n = 1) + { + if (!reg) { + return fs_reg(); + } else { + return fs_reg(retype(brw_vec8_grf(reg, 0), type)); + } + } +} + void shuffle_from_32bit_read(const brw::fs_builder &bld, const fs_reg &dst, const fs_reg &src, diff --git a/src/intel/compiler/brw_fs_visitor.cpp b/src/intel/compiler/brw_fs_visitor.cpp index c165fba5b68..a0ebd607e46 100644 --- a/src/intel/compiler/brw_fs_visitor.cpp +++ b/src/intel/compiler/brw_fs_visitor.cpp @@ -258,7 +258,7 @@ fs_visitor::emit_interpolation_setup_gen6() } abld = bld.annotate("compute pos.w"); - this->pixel_w = fs_reg(brw_vec8_grf(payload.source_w_reg, 0)); + this->pixel_w = fetch_payload_reg(abld, payload.source_w_reg); this->wpos_w = vgrf(glsl_type::float_type); abld.emit(SHADER_OPCODE_RCP, this->wpos_w, this->pixel_w); @@ -268,8 +268,8 @@ fs_visitor::emit_interpolation_setup_gen6() 1 << BRW_BARYCENTRIC_NONPERSPECTIVE_CENTROID); for (int i = 0; i < BRW_BARYCENTRIC_MODE_COUNT; ++i) { - this->delta_xy[i] = - fs_reg(brw_vec8_grf(payload.barycentric_coord_reg[i], 0)); + this->delta_xy[i] = fetch_payload_reg( + bld, payload.barycentric_coord_reg[i], BRW_REGISTER_TYPE_F, 2); if (devinfo->needs_unlit_centroid_workaround && (centroid_modes & (1 << i))) { @@ -363,16 +363,14 @@ fs_visitor::emit_single_fb_write(const fs_builder &bld, struct brw_wm_prog_data *prog_data = brw_wm_prog_data(this->prog_data); /* Hand over gl_FragDepth or the payload depth. */ - const fs_reg dst_depth = (payload.dest_depth_reg ? - fs_reg(brw_vec8_grf(payload.dest_depth_reg, 0)) : - fs_reg()); + const fs_reg dst_depth = fetch_payload_reg(bld, payload.dest_depth_reg); fs_reg src_depth, src_stencil; if (source_depth_to_render_target) { if (nir->info.outputs_written & BITFIELD64_BIT(FRAG_RESULT_DEPTH)) src_depth = frag_depth; else - src_depth = fs_reg(brw_vec8_grf(payload.source_depth_reg, 0)); + src_depth = fetch_payload_reg(bld, payload.source_depth_reg); } if (nir->info.outputs_written & BITFIELD64_BIT(FRAG_RESULT_STENCIL))