From: lkcl <lkcl@web>
Date: Mon, 22 May 2023 15:05:12 +0000 (+0100)
Subject: (no commit message)
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=8f2dabab639e116eb2a6e19b276e3740aa385bb9;p=libreriscv.git

---

diff --git a/openpower/sv/svp64.mdwn b/openpower/sv/svp64.mdwn
index c3d2362d1..06129bd7b 100644
--- a/openpower/sv/svp64.mdwn
+++ b/openpower/sv/svp64.mdwn
@@ -72,7 +72,7 @@ Branch-Conditional operations and LD/ST-update "Post-Increment"
 Mode.  Post-Increment was considered sufficiently high priority
 (significantly reducing hot-loop instruction count) that one bit in
 the Prefix is reserved for it (*Note the intention to release that bit
-and move Post-Increment instructions to EXT2xx, as part of [[ls011]]*).
+and move Post-Increment instructions to EXT2xx, as part of [[sv/rfc/ls011]]*).
 Vectorised Branch-Conditional operations "embed" the original Scalar
 Branch-Conditional behaviour into a much more advanced variant that is
 highly suited to High-Performance Computation (HPC), Supercomputing,