From: Andrew Waterman <andrew@sifive.com>
Date: Tue, 28 Mar 2017 04:21:57 +0000 (-0700)
Subject: On EBREAK, set badaddr to pc
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=8f4fb411b016846a539a1ff1cd645a555e3737be;p=riscv-isa-sim.git

On EBREAK, set badaddr to pc
---

diff --git a/riscv/insns/c_ebreak.h b/riscv/insns/c_ebreak.h
index a17200f..128b86b 100644
--- a/riscv/insns/c_ebreak.h
+++ b/riscv/insns/c_ebreak.h
@@ -1,2 +1,2 @@
 require_extension('C');
-throw trap_breakpoint();
+throw trap_breakpoint(pc);
diff --git a/riscv/insns/ebreak.h b/riscv/insns/ebreak.h
index c22776c..736cebe 100644
--- a/riscv/insns/ebreak.h
+++ b/riscv/insns/ebreak.h
@@ -1 +1 @@
-throw trap_breakpoint();
+throw trap_breakpoint(pc);
diff --git a/riscv/trap.h b/riscv/trap.h
index a289a68..20313e9 100644
--- a/riscv/trap.h
+++ b/riscv/trap.h
@@ -47,7 +47,7 @@ class mem_trap_t : public trap_t
 DECLARE_MEM_TRAP(CAUSE_MISALIGNED_FETCH, instruction_address_misaligned)
 DECLARE_MEM_TRAP(CAUSE_FETCH_ACCESS, instruction_access_fault)
 DECLARE_TRAP(CAUSE_ILLEGAL_INSTRUCTION, illegal_instruction)
-DECLARE_TRAP(CAUSE_BREAKPOINT, breakpoint)
+DECLARE_MEM_TRAP(CAUSE_BREAKPOINT, breakpoint)
 DECLARE_MEM_TRAP(CAUSE_MISALIGNED_LOAD, load_address_misaligned)
 DECLARE_MEM_TRAP(CAUSE_MISALIGNED_STORE, store_address_misaligned)
 DECLARE_MEM_TRAP(CAUSE_LOAD_ACCESS, load_access_fault)