From: Luke Kenneth Casson Leighton Date: Mon, 4 May 2020 09:31:15 +0000 (+0100) Subject: better comments on rd/wr pending X-Git-Tag: div_pipeline~1397 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=8f5213b007e5a42e34a4743648ec3cd7d6980372;p=soc.git better comments on rd/wr pending --- diff --git a/src/soc/scoremulti/fu_reg_matrix.py b/src/soc/scoremulti/fu_reg_matrix.py index 5c87676a..a4b66f5a 100644 --- a/src/soc/scoremulti/fu_reg_matrix.py +++ b/src/soc/scoremulti/fu_reg_matrix.py @@ -80,11 +80,15 @@ class FURegDepMatrix(Elaboratable): self.src_rsel_o = Array(rsel) # src reg (bot) # for Function Unit "forward progress" (vertical), per-FU - self.wr_pend_o = Signal(n_fu_row, reset_less=True) # wr pending (right) + + # global "merged" (all regs) src/dest pending vectors self.wr_dst_pend_o = Array(wpnd) # dest pending - self.rd_pend_o = Signal(n_fu_row, reset_less=True) # rd pending (right) self.rd_src_pend_o = Array(pend) # src1 pending + # per-port src/dest pending vectors + self.wr_pend_o = Signal(n_fu_row, reset_less=True) # wr pending (right) + self.rd_pend_o = Signal(n_fu_row, reset_less=True) # rd pending (right) + def elaborate(self, platform): m = Module() return self._elaborate(m, platform)