From: lkcl <lkcl@web>
Date: Tue, 19 Apr 2022 12:09:00 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: opf_rfc_ls005_v1~2706
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=8f567ee9f4a80cd68a07a1339d31f5e98136bd27;p=libreriscv.git

---

diff --git a/openpower/isa/svfixedarith.mdwn b/openpower/isa/svfixedarith.mdwn
index e51e292b2..1cb17ac42 100644
--- a/openpower/isa/svfixedarith.mdwn
+++ b/openpower/isa/svfixedarith.mdwn
@@ -32,15 +32,19 @@ Special Registers Altered:
 
 # Twin Multiply and Add  Doubleword
 
-<!-- SVP64: RC-as-source and RC-as-dest have separate EXTRA2 -->
-<!-- RT, RA have EXTRA2 marking. RB is always scalar (r0-31) -->
 * maddx RT,RA,RB,RC
 
+    <!-- SVP64: RC-as-source and RC-as-dest have separate EXTRA2 -->
+    <!-- RT, RA have EXTRA2 marking. RB is always scalar (r0-31) -->
     prod[0:127] <- (RA) * (RB)
     sum[0:127] <- EXTZ(RC) + prod
     RT <- sum[64:127]
     RC <- sum[0:63]
 
+Special Registers Altered:
+
+    None
+
 # Twin Multiply and Subtract Doubleword
 
 * msubx RT,RA,RB,RC