From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 27 Sep 2019 22:14:31 +0000 (-0700)
Subject: Merge remote-tracking branch 'origin/master' into xaig_dff
X-Git-Tag: working-ls180~881^2^2~212
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=8f5710c464b2b3b91f0c7f29a9420dcb798be4c5;p=yosys.git

Merge remote-tracking branch 'origin/master' into xaig_dff
---

8f5710c464b2b3b91f0c7f29a9420dcb798be4c5
diff --cc passes/techmap/abc9.cc
index 29929f80b,7eac08d17..97d4c5ef3
--- a/passes/techmap/abc9.cc
+++ b/passes/techmap/abc9.cc
@@@ -570,17 -536,19 +535,19 @@@ void abc9_module(RTLIL::Design *design
  		dict<SigBit, std::vector<RTLIL::Cell*>> bit2sinks;
  
  		std::map<IdString, int> cell_stats;
 -		for (auto c : mapped_mod->cells())
 +		for (auto mapped_cell : mapped_mod->cells())
  		{
 -			toposort.node(c->name);
 +			toposort.node(mapped_cell->name);
  
  			RTLIL::Cell *cell = nullptr;
 -			if (c->type == ID($_NOT_)) {
 -				RTLIL::SigBit a_bit = c->getPort(ID::A);
 -				RTLIL::SigBit y_bit = c->getPort(ID::Y);
 -				bit_users[a_bit].insert(c->name);
 -				bit_drivers[y_bit].insert(c->name);
 +			if (mapped_cell->type == ID($_NOT_)) {
 +				RTLIL::SigBit a_bit = mapped_cell->getPort(ID::A);
 +				RTLIL::SigBit y_bit = mapped_cell->getPort(ID::Y);
++				bit_users[a_bit].insert(mapped_cell->name);
++				bit_drivers[y_bit].insert(mapped_cell->name);
  
  				if (!a_bit.wire) {
 -					c->setPort(ID::Y, module->addWire(NEW_ID));
 +					mapped_cell->setPort(ID::Y, module->addWire(NEW_ID));
  					RTLIL::Wire *wire = module->wire(remap_name(y_bit.wire->name));
  					log_assert(wire);
  					module->connect(RTLIL::SigBit(wire, y_bit.offset), State::S1);
@@@ -598,25 -566,25 +565,25 @@@
  							driver_name = stringf("%s$lut", a_bit.wire->name.c_str());
  						else
  							driver_name = stringf("%s[%d]$lut", a_bit.wire->name.c_str(), a_bit.offset);
- 						driving_lut = mapped_mod->cell(driver_name);
+ 						driver_lut = mapped_mod->cell(driver_name);
  					}
  
- 					if (!driving_lut) {
+ 					if (!driver_lut) {
  						// If a driver couldn't be found (could be from PI or box CI)
  						// then implement using a LUT
 -						cell = module->addLut(remap_name(stringf("%s$lut", c->name.c_str())),
 +						cell = module->addLut(remap_name(stringf("%s$lut", mapped_cell->name.c_str())),
  								RTLIL::SigBit(module->wires_.at(remap_name(a_bit.wire->name)), a_bit.offset),
  								RTLIL::SigBit(module->wires_.at(remap_name(y_bit.wire->name)), y_bit.offset),
  								RTLIL::Const::from_string("01"));
  						bit2sinks[cell->getPort(ID::A)].push_back(cell);
  						cell_stats[ID($lut)]++;
- 						bit_users[a_bit].insert(mapped_cell->name);
- 						bit_drivers[y_bit].insert(mapped_cell->name);
  					}
  					else
- 						not2drivers[mapped_cell] = driving_lut;
 -						not2drivers[c] = driver_lut;
++						not2drivers[mapped_cell] = driver_lut;
  					continue;
  				}
+ 				else
+ 					log_abort();
  				if (cell && markgroups) cell->attributes[ID(abcgroup)] = map_autoidx;
  				continue;
  			}
@@@ -1170,15 -1116,9 +1119,16 @@@ struct Abc9Pass : public Pass 
  			assign_map.set(mod);
  
  			if (!dff_mode || !clk_str.empty()) {
 -				abc9_module(design, mod, script_file, exe_file, cleanup, lut_costs, dff_mode, clk_str, keepff,
 +
 +				design->selection_stack.emplace_back(false);
 +				RTLIL::Selection& sel = design->selection_stack.back();
 +				sel.select(mod);
 +
 +				abc9_module(design, mod, script_file, exe_file, cleanup, lut_costs, false, clk_str, keepff,
  						delay_target, lutin_shared, fast_mode, show_tempdir,
- 						box_file, lut_file, wire_delay, box_lookup, scc_break_inputs);
+ 						box_file, lut_file, wire_delay, box_lookup);
++
 +				design->selection_stack.pop_back();
  				continue;
  			}
  
diff --cc techlibs/xilinx/abc_model.v
index 7162bd213,655b993f6..d94ddb7e5
--- a/techlibs/xilinx/abc_model.v
+++ b/techlibs/xilinx/abc_model.v
@@@ -26,154 -26,9 +26,97 @@@ module \$__XILINX_MUXF78 (output O, inp
                  : (S0 ? I1 : I0);
  endmodule
  
 +module \$__ABC_FF_ (input C, D, output Q);
 +endmodule
 +
 +(* abc_box_id = 1000 *)
 +module \$__ABC_ASYNC (input A, S, output Y);
 +endmodule
 +
 +(* abc_box_id=1001, lib_whitebox, abc_flop *)
 +module \$__ABC_FDRE ((* abc_flop_q, abc_arrival=303 *) output Q,
 +                     (* abc_flop_clk *) input C,
 +                     (* abc_flop_en *)  input CE,
 +                     (* abc_flop_d *)   input D,
 +                     input R, \$pastQ );
 +  parameter [0:0] INIT = 1'b0;
 +  parameter [0:0] IS_C_INVERTED = 1'b0;
 +  parameter [0:0] IS_D_INVERTED = 1'b0;
 +  parameter [0:0] IS_R_INVERTED = 1'b0;
 +  parameter CLK_POLARITY = !IS_C_INVERTED;
 +  parameter EN_POLARITY = 1'b1;
 +  assign Q = (R ^ IS_R_INVERTED) ? 1'b0 : (CE ? (D ^ IS_D_INVERTED) : \$pastQ );
 +endmodule
 +
 +(* abc_box_id=1002, lib_whitebox, abc_flop *)
 +module \$__ABC_FDRE_1 ((* abc_flop_q, abc_arrival=303 *) output Q,
 +                       (* abc_flop_clk *) input C,
 +                       (* abc_flop_en *)  input CE,
 +                       (* abc_flop_d *)   input D,
 +                       input R, \$pastQ );
 +  parameter [0:0] INIT = 1'b0;
 +  parameter CLK_POLARITY = 1'b0;
 +  parameter EN_POLARITY = 1'b1;
 +  assign Q = R ? 1'b0 : (CE ? D : \$pastQ );
 +endmodule
 +
 +(* abc_box_id=1003, lib_whitebox, abc_flop *)
 +module \$__ABC_FDCE ((* abc_flop_q, abc_arrival=303 *) output Q,
 +                     (* abc_flop_clk *) input C,
 +                     (* abc_flop_en *)  input CE,
 +                     (* abc_flop_d *)   input D,
 +                     input CLR, \$pastQ );
 +  parameter [0:0] INIT = 1'b0;
 +  parameter [0:0] IS_C_INVERTED = 1'b0;
 +  parameter [0:0] IS_D_INVERTED = 1'b0;
 +  parameter [0:0] IS_CLR_INVERTED = 1'b0;
 +  parameter CLK_POLARITY = !IS_C_INVERTED;
 +  parameter EN_POLARITY = 1'b1;
 +  assign Q = (CE && !(CLR ^ IS_CLR_INVERTED)) ? (D ^ IS_D_INVERTED) : \$pastQ ;
 +endmodule
 +
 +(* abc_box_id=1004, lib_whitebox, abc_flop *)
 +module \$__ABC_FDCE_1 ((* abc_flop_q, abc_arrival=303 *) output Q,
 +                       (* abc_flop_clk *) input C,
 +                       (* abc_flop_en *)  input CE,
 +                       (* abc_flop_d *)   input D,
 +                       input CLR, \$pastQ );
 +  parameter [0:0] INIT = 1'b0;
 +  parameter CLK_POLARITY = 1'b0;
 +  parameter EN_POLARITY = 1'b1;
 +  assign Q = (CE && !CLR) ? D : \$pastQ ;
 +endmodule
 +
 +(* abc_box_id=1005, lib_whitebox, abc_flop *)
 +module \$__ABC_FDPE ((* abc_flop_q, abc_arrival=303 *) output Q,
 +                     (* abc_flop_clk *) input C,
 +                     (* abc_flop_en *)  input CE,
 +                     (* abc_flop_d *)   input D,
 +                     input PRE, \$pastQ );
 +  parameter [0:0] INIT = 1'b0;
 +  parameter [0:0] IS_C_INVERTED = 1'b0;
 +  parameter [0:0] IS_D_INVERTED = 1'b0;
 +  parameter [0:0] IS_PRE_INVERTED = 1'b0;
 +  parameter CLK_POLARITY = !IS_C_INVERTED;
 +  parameter EN_POLARITY = 1'b1;
 +  assign Q = (CE && !(PRE ^ IS_PRE_INVERTED)) ? (D ^ IS_D_INVERTED) : \$pastQ ;
 +endmodule
 +
 +(* abc_box_id=1006, lib_whitebox, abc_flop *)
 +module \$__ABC_FDPE_1 ((* abc_flop_q, abc_arrival=303 *) output Q,
 +                       (* abc_flop_clk *) input C,
 +                       (* abc_flop_en *)  input CE,
 +                       (* abc_flop_d *)   input D,
 +                       input PRE, \$pastQ );
 +  parameter [0:0] INIT = 1'b0; 
 +  parameter CLK_POLARITY = 1'b0;
 +  parameter EN_POLARITY = 1'b1;
 +  assign Q = (CE && !PRE) ? D : \$pastQ ;
 +endmodule
 +
  (* abc_box_id=2000 *)
- module \$__ABC_LUTMUX6 (input A, input [5:0] S, output Y);
+ module \$__ABC_LUT6 (input A, input [5:0] S, output Y);
  endmodule
  (* abc_box_id=2001 *)
- module \$__ABC_LUTMUX7 (input A, input [6:0] S, output Y);
- endmodule
- 
- 
- module \$__ABC_RAM32X1D (
-   // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L957
-   (* abc_arrival=1153 *) output DPO, SPO,
-   input  D,
-   input  WCLK,
-   input  WE,
-   input  A0, A1, A2, A3, A4,
-   input  DPRA0, DPRA1, DPRA2, DPRA3, DPRA4
- );
- endmodule
- 
- module \$__ABC_RAM64X1D (
-   // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L957
-   (* abc_arrival=1153 *) output DPO, SPO,
-   input  D,
-   input  WCLK,
-   input  WE,
-   input  A0, A1, A2, A3, A4, A5,
-   input  DPRA0, DPRA1, DPRA2, DPRA3, DPRA4, DPRA5
- );
-   parameter INIT = 64'h0;
-   parameter IS_WCLK_INVERTED = 1'b0;
- endmodule
- 
- module \$__ABC_RAM128X1D (
-   // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L957
-   (* abc_arrival=1153 *) output DPO, SPO,
-   input        D,
-   input        WCLK,
-   input        WE,
-   input  [6:0] A, DPRA
- );
-   parameter INIT = 128'h0;
-   parameter IS_WCLK_INVERTED = 1'b0;
- endmodule
- 
- module SRL16E (
-   // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L904-L905
-   (* abc_arrival=1472 *) output Q,
-   input A0, A1, A2, A3, CE, CLK, D
- );
-   parameter [15:0] INIT = 16'h0000;
-   parameter [0:0] IS_CLK_INVERTED = 1'b0;
- endmodule
- 
- module SRLC32E (
-   // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L904-L905
-   (* abc_arrival=1472 *) output Q,
-   (* abc_arrival=1114 *) output Q31,
-   input [4:0] A,
-   input CE, CLK, D
- );
-   parameter [31:0] INIT = 32'h00000000;
-   parameter [0:0] IS_CLK_INVERTED = 1'b0;
+ module \$__ABC_LUT7 (input A, input [6:0] S, output Y);
  endmodule
diff --cc techlibs/xilinx/abc_unmap.v
index d00d27e2e,f101a22d0..c24571747
--- a/techlibs/xilinx/abc_unmap.v
+++ b/techlibs/xilinx/abc_unmap.v
@@@ -20,220 -20,9 +20,128 @@@
  
  // ============================================================================
  
 +module \$__ABC_ASYNC (input A, S, output Y);
 +  assign Y = A;
 +endmodule
 +
 +module \$__ABC_FDRE (output Q,
 +                     input C,
 +                     input CE,
 +                     input D,
 +                     input R, \$pastQ );
 +  parameter [0:0] INIT = 1'b0;
 +  parameter [0:0] IS_C_INVERTED = 1'b0;
 +  parameter [0:0] IS_D_INVERTED = 1'b0;
 +  parameter [0:0] IS_R_INVERTED = 1'b0;
 +  parameter CLK_POLARITY = !IS_C_INVERTED;
 +  parameter EN_POLARITY = 1'b1;
 +
 +  FDRE #(
 +    .INIT(INIT),
 +    .IS_C_INVERTED(IS_C_INVERTED),
 +    .IS_D_INVERTED(IS_D_INVERTED),
 +    .IS_R_INVERTED(IS_R_INVERTED),
 +  ) _TECHMAP_REPLACE_ (
 +    .D(D), .Q(Q), .C(C), .CE(CE), .R(R)
 +  );
 +endmodule
 +
 +module \$__ABC_FDRE_1 (output Q,
 +                       input C,
 +                       input CE,
 +                       input D,
 +                       input R, \$pastQ );
 +  parameter [0:0] INIT = 1'b0;
 +  parameter CLK_POLARITY = 1'b0;
 +  parameter EN_POLARITY = 1'b1;
 +  assign Q = R ? 1'b0 : (CE ? D : \$pastQ );
 +
 +  FDRE_1 #(
 +    .INIT(INIT),
 +  ) _TECHMAP_REPLACE_ (
 +    .D(D), .Q(Q), .C(C), .CE(CE), .R(R)
 +  );
 +endmodule
 +
 +module \$__ABC_FDCE (output Q,
 +                     input C,
 +                     input CE,
 +                     input D,
 +                     input CLR, \$pastQ );
 +  parameter [0:0] INIT = 1'b0;
 +  parameter [0:0] IS_C_INVERTED = 1'b0;
 +  parameter [0:0] IS_D_INVERTED = 1'b0;
 +  parameter [0:0] IS_CLR_INVERTED = 1'b0;
 +  parameter CLK_POLARITY = !IS_C_INVERTED;
 +  parameter EN_POLARITY = 1'b1;
 +
 +  FDCE #(
 +    .INIT(INIT),
 +    .IS_C_INVERTED(IS_C_INVERTED),
 +    .IS_D_INVERTED(IS_D_INVERTED),
 +    .IS_CLR_INVERTED(IS_CLR_INVERTED),
 +  ) _TECHMAP_REPLACE_ (
 +    .D(D), .Q(Q), .C(C), .CE(CE), .CLR(CLR)
 +  );
 +endmodule
 +
 +module \$__ABC_FDCE_1 (output Q,
 +                       input C,
 +                       input CE,
 +                       input D,
 +                       input CLR, \$pastQ );
 +  parameter [0:0] INIT = 1'b0;
 +  parameter CLK_POLARITY = 1'b0;
 +  parameter EN_POLARITY = 1'b1;
 +
 +  FDCE_1 #(
 +    .INIT(INIT),
 +  ) _TECHMAP_REPLACE_ (
 +    .D(D), .Q(Q), .C(C), .CE(CE), .CLR(CLR)
 +  );
 +endmodule
 +
 +module \$__ABC_FDPE (output Q,
 +                     input C,
 +                     input CE,
 +                     input D,
 +                     input PRE, \$pastQ );
 +  parameter [0:0] INIT = 1'b0;
 +  parameter [0:0] IS_C_INVERTED = 1'b0;
 +  parameter [0:0] IS_D_INVERTED = 1'b0;
 +  parameter [0:0] IS_PRE_INVERTED = 1'b0;
 +  parameter CLK_POLARITY = !IS_C_INVERTED;
 +  parameter EN_POLARITY = 1'b1;
 +
 +  FDPE #(
 +    .INIT(INIT),
 +    .IS_C_INVERTED(IS_C_INVERTED),
 +    .IS_D_INVERTED(IS_D_INVERTED),
 +    .IS_PRE_INVERTED(IS_PRE_INVERTED),
 +  ) _TECHMAP_REPLACE_ (
 +    .D(D), .Q(Q), .C(C), .CE(CE), .PRE(PRE)
 +  );
 +endmodule
 +
 +module \$__ABC_FDPE_1 (output Q,
 +                       input C,
 +                       input CE,
 +                       input D,
 +                       input PRE, \$pastQ );
 +  parameter [0:0] INIT = 1'b0;
 +  parameter CLK_POLARITY = 1'b0;
 +  parameter EN_POLARITY = 1'b1;
 +
 +  FDPE_1 #(
 +    .INIT(INIT),
 +  ) _TECHMAP_REPLACE_ (
 +    .D(D), .Q(Q), .C(C), .CE(CE), .PRE(PRE)
 +  );
 +endmodule
 +
- module \$__ABC_LUTMUX6 (input A, input [5:0] S, output Y);
+ module \$__ABC_LUT6 (input A, input [5:0] S, output Y);
    assign Y = A;
  endmodule
- module \$__ABC_LUTMUX7 (input A, input [6:0] S, output Y);
+ module \$__ABC_LUT7 (input A, input [6:0] S, output Y);
    assign Y = A;
  endmodule
- 
- module \$__ABC_RAM32X1D (
-   output DPO, SPO,
-   input  D,
-   input  WCLK,
-   input  WE,
-   input  A0, A1, A2, A3, A4,
-   input  DPRA0, DPRA1, DPRA2, DPRA3, DPRA4
- );
-   parameter INIT = 32'h0;
-   parameter IS_WCLK_INVERTED = 1'b0;
-   RAM32X1D #(
-     .INIT(INIT), .IS_WCLK_INVERTED(IS_WCLK_INVERTED)
-   ) _TECHMAP_REPLACE_ (
-     .DPO(DPO), .SPO(SPO),
-     .D(D), .WCLK(WCLK), .WE(WE),
-     .A0(A0), .A1(A1), .A2(A2), .A3(A3), .A4(A4),
-     .DPRA0(DPRA0), .DPRA1(DPRA1), .DPRA2(DPRA2), .DPRA3(DPRA3), .DPRA4(DPRA4)
-   );
- endmodule
- 
- module \$__ABC_RAM64X1D (
-   output DPO, SPO,
-   input  D,
-   input  WCLK,
-   input  WE,
-   input  A0, A1, A2, A3, A4, A5,
-   input  DPRA0, DPRA1, DPRA2, DPRA3, DPRA4, DPRA5
- );
-   parameter INIT = 64'h0;
-   parameter IS_WCLK_INVERTED = 1'b0;
-   RAM64X1D #(
-     .INIT(INIT), .IS_WCLK_INVERTED(IS_WCLK_INVERTED)
-   ) _TECHMAP_REPLACE_ (
-     .DPO(DPO), .SPO(SPO),
-     .D(D), .WCLK(WCLK), .WE(WE),
-     .A0(A0), .A1(A1), .A2(A2), .A3(A3), .A4(A4), .A5(A5),
-     .DPRA0(DPRA0), .DPRA1(DPRA1), .DPRA2(DPRA2), .DPRA3(DPRA3), .DPRA4(DPRA4), .DPRA5(DPRA5)
-   );
- endmodule
- 
- module \$__ABC_RAM128X1D (
-   output DPO, SPO,
-   input  D,
-   input  WCLK,
-   input  WE,
-   input  A,
-   input  DPRA,
- );
-   parameter INIT = 128'h0;
-   parameter IS_WCLK_INVERTED = 1'b0;
-   RAM128X1D #(
-     .INIT(INIT), .IS_WCLK_INVERTED(IS_WCLK_INVERTED)
-   ) _TECHMAP_REPLACE_ (
-     .DPO(DPO), .SPO(SPO),
-     .D(D), .WCLK(WCLK), .WE(WE),
-     .A(A),
-     .DPRA(DPRA)
-   );
- endmodule
- 
- module \$__ABC_SRL16E (
-   output Q,
-   input A0, A1, A2, A3, CE, CLK, D
- );
-   parameter [15:0] INIT = 16'h0000;
-   parameter [0:0] IS_CLK_INVERTED = 1'b0;
- 
-   SRL16E #(
-     .INIT(INIT), .IS_CLK_INVERTED(IS_CLK_INVERTED)
-   ) _TECHMAP_REPLACE_ (
-     .Q(Q),
-     .A0(A0), .A1(A1), .A2(A2), .A3(A3), .CE(CE), .CLK(CLK), .D(D)
-   );
- endmodule
- 
- module \$__ABC_SRLC32E (
-   output Q,
-   output Q31,
-   input [4:0] A,
-   input CE, CLK, D
- );
-   parameter [31:0] INIT = 32'h00000000;
-   parameter [0:0] IS_CLK_INVERTED = 1'b0;
- 
-   SRLC32E #(
-     .INIT(INIT), .IS_CLK_INVERTED(IS_CLK_INVERTED)
-   ) _TECHMAP_REPLACE_ (
-     .Q(Q), .Q31(Q31),
-     .A(A), .CE(CE), .CLK(CLK), .D(D)
-   );
- endmodule
diff --cc techlibs/xilinx/abc_xc7.box
index c08af6320,20da3b8a0..aebb8b975
--- a/techlibs/xilinx/abc_xc7.box
+++ b/techlibs/xilinx/abc_xc7.box
@@@ -38,52 -41,16 +41,57 @@@ CARRY4 4 1 10 
  592 540 520 356 -   512 548 292 -   228
  580 526 507 398 385 508 528 378 380 114
  
 +# Box to emulate async behaviour of FD[CP]*
 +# Inputs: A S
 +# Outputs: Y
 +$__ABC_ASYNC 1000 0 2 1
 +0 764
 +
 +# The following FD*.{CE,R,CLR,PRE) are offset by 46ps to
 +# reflect the -46ps Tsu
 +# https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L237-L251
 +# https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L265-L277
 +
 +# Inputs: C CE D R \$pastQ
 +# Outputs: Q
 +FDRE 1001 1 5 1
 +0 151 0 446 0
 +
 +# Inputs: C CE D R \$pastQ
 +# Outputs: Q
 +FDRE_1 1002 1 5 1
 +0 151 0 446 0
 +
 +# Inputs: C CE CLR D \$pastQ
 +# Outputs: Q
 +FDCE 1003 1 5 1
 +0 151 806 0 0
 +
 +# Inputs: C CE CLR D \$pastQ
 +# Outputs: Q
 +FDCE_1 1004 1 5 1
 +0 151 806 0 0
 +
 +# Inputs: C CE D PRE \$pastQ
 +# Outputs: Q
 +FDPE 1005 1 5 1
 +0 151 0 806 0
 +
 +# Inputs: C CE D PRE \$pastQ
 +# Outputs: Q
 +FDPE_1 1006 1 5 1
 +0 151 0 806 0
 +
  # SLICEM/A6LUT
  # Box to emulate comb/seq behaviour of RAMD{32,64} and SRL{16,32}
+ #   Necessary since RAMD* and SRL* have both combinatorial (i.e.
+ #   same-cycle read operation) and sequential (write operation
+ #   is only committed on the next clock edge).
+ #   To model the combinatorial path, such cells have to be split
+ #   into comb and seq parts, with this box modelling only the former.
  # Inputs: A S0 S1 S2 S3 S4 S5
  # Outputs: Y
- $__ABC_LUTRAM6 2000 0 7 1
+ $__ABC_LUT6 2000 0 7 1
  0 642 631 472 407 238 127
  
  # SLICEM/A6LUT + F7BMUX