From: Stephen Twigg <sdtwigg@eecs.berkeley.edu>
Date: Wed, 9 Apr 2014 04:53:19 +0000 (-0700)
Subject: Adjust hwacha misaligned instruction test to ignore lower 2 bits in comparisons to... 
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=8f6e2420926471a7bd9a660305ab3d6a22f22dc9;p=riscv-tests.git

Adjust hwacha misaligned instruction test to ignore lower 2 bits in comparisons to account for impl differences.
---

diff --git a/isa/rv64sv/ma_vt_inst.S b/isa/rv64sv/ma_vt_inst.S
index cd7762d..d772041 100644
--- a/isa/rv64sv/ma_vt_inst.S
+++ b/isa/rv64sv/ma_vt_inst.S
@@ -48,6 +48,8 @@ handler:
   # check badvaddr
   vxcptaux a3
   la a4,vtcode1+2
+  andi a3, a3, -4 # mask off lower bits so that may
+  andi a4, a4, -4 # ignore impl. specific behavior
   bne a3,a4,fail
 
   # make sure vector unit has cleared out