From: Luke Kenneth Casson Leighton Date: Sun, 30 Apr 2023 19:08:19 +0000 (+0100) Subject: ffnmadds converted to 3-operand X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=8f6f766886c3bb03d92762ae06f761ec39ba28c1;p=openpower-isa.git ffnmadds converted to 3-operand --- diff --git a/openpower/isa/svfparith.mdwn b/openpower/isa/svfparith.mdwn index bdb732af..b6066f8f 100644 --- a/openpower/isa/svfparith.mdwn +++ b/openpower/isa/svfparith.mdwn @@ -243,13 +243,14 @@ Special Registers Altered: A-Form -* ffnmsubs FRT,FRA,FRC,FRB (Rc=0) -* ffnmsubs. FRT,FRA,FRC,FRB (Rc=1) +* ffnmsubs FRT,FRA,FRB (Rc=0) +* ffnmsubs. FRT,FRA,FRB (Rc=1) Pseudo-code: - FRT <- FPMULADD32(FRA, FRC, FRB, -1, 1) - FRS <- FPMULADD32(FRA, FRC, FRB, 1, 1) + tmp <- FRT + FRT <- FPMULADD32(tmp, FRA, FRB, -1, 1) + FRS <- FPMULADD32(tmp, FRA, FRB, 1, 1) Special Registers Altered: diff --git a/openpower/isatables/minor_59.csv b/openpower/isatables/minor_59.csv index 7cd33d9b..14fb4eb3 100644 --- a/openpower/isatables/minor_59.csv +++ b/openpower/isatables/minor_59.csv @@ -16,7 +16,7 @@ opcode,unit,internal op,in1,in2,in3,out,CR in,CR out,inv A,inv out,cry in,cry ou -----11111,FPU,OP_FP_MADD,FRA,FRB,FRC,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,1,0,RC_ONLY,0,0,fnmadds,A,,, -----00100,FPU,OP_FP_MADD,FRT,FRB,FRA,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,1,0,RC_ONLY,0,0,ffmsubs,A,,1,3-in 2-out: implicit FRS. unofficial until submitted and approved/renumbered by the opf isa wg -----00101,FPU,OP_FP_MADD,FRT,FRB,FRA,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,1,0,RC_ONLY,0,0,ffmadds,A,,1,3-in 2-out: implicit FRS. unofficial until submitted and approved/renumbered by the opf isa wg ------00110,FPU,OP_FP_MADD,FRA,FRB,FRC,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,1,0,RC_ONLY,0,0,ffnmsubs,A,,1,3-in 2-out: implicit FRS. unofficial until submitted and approved/renumbered by the opf isa wg +-----00110,FPU,OP_FP_MADD,FRT,FRB,FRA,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,1,0,RC_ONLY,0,0,ffnmsubs,A,,1,3-in 2-out: implicit FRS. unofficial until submitted and approved/renumbered by the opf isa wg -----00111,FPU,OP_FP_MADD,FRT,FRB,FRA,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,1,0,RC_ONLY,0,0,ffnmadds,A,,1,3-in 2-out: implicit FRS. unofficial until submitted and approved/renumbered by the opf isa wg 1111100000,FPU,OP_FPOP,FRA,FRB,NONE,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,1,0,RC_ONLY,0,0,ffadds,X,,1,2-in 2-out: implicit FRS. unofficial until submitted and approved/renumbered by the opf isa wg -----11011,FPU,OP_FP_MADD,FRT,FRB,FRA,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,1,0,RC_ONLY,0,0,fdmadds,DCT,,1,3-in 2-out: implicit FRS. unofficial until submitted and approved/renumbered by the opf isa wg