From: Segher Boessenkool Date: Mon, 30 Jul 2018 17:50:26 +0000 (+0200) Subject: arm: Generate correct const_ints (PR86640) X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=8f953899e38f92e8f4cdeaffaa04f8a9e69a7726;p=gcc.git arm: Generate correct const_ints (PR86640) In arm_block_set_aligned_vect 8-bit constants are generated as zero- extended const_ints, not sign-extended as required. Fix that. PR target/86640 * config/arm/arm.c (arm_block_set_aligned_vect): Use gen_int_mode instead of GEN_INT. From-SVN: r263075 --- diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 20781df77c7..0616687f5d9 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,9 @@ +2018-07-30 Segher Boessenkool + + PR target/86640 + * config/arm/arm.c (arm_block_set_aligned_vect): Use gen_int_mode + instead of GEN_INT. + 2018-07-30 Bernd Edlinger * tree-ssa-forwprop.c (simplify_builtin_call): Don't create a not NUL diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c index cf12aceb5fd..f5eece4f152 100644 --- a/gcc/config/arm/arm.c +++ b/gcc/config/arm/arm.c @@ -30046,7 +30046,6 @@ arm_block_set_aligned_vect (rtx dstbase, rtx dst, addr, mem; rtx val_vec, reg; machine_mode mode; - unsigned HOST_WIDE_INT v = value; unsigned int offset = 0; gcc_assert ((align & 0x3) == 0); @@ -30065,10 +30064,8 @@ arm_block_set_aligned_vect (rtx dstbase, dst = copy_addr_to_reg (XEXP (dstbase, 0)); - v = sext_hwi (v, BITS_PER_WORD); - reg = gen_reg_rtx (mode); - val_vec = gen_const_vec_duplicate (mode, GEN_INT (v)); + val_vec = gen_const_vec_duplicate (mode, gen_int_mode (value, QImode)); /* Emit instruction loading the constant value. */ emit_move_insn (reg, val_vec);