From: Shriya Sharma <shriya@redsemiconductor.com>
Date: Thu, 19 Oct 2023 10:16:53 +0000 (+0100)
Subject: added lbzsux instruction refer to  https://bugs.libre-soc.org/show_bug.cgi?id=1055
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=8f9616f27226ec6ebb84d50ca1d40e4dd43bb2ea;p=openpower-isa.git

added lbzsux instruction refer to  https://bugs.libre-soc.org/show_bug.cgi?id=1055
---

diff --git a/openpower/isa/fixedloadshift.mdwn b/openpower/isa/fixedloadshift.mdwn
index bc488ad0..45827e77 100644
--- a/openpower/isa/fixedloadshift.mdwn
+++ b/openpower/isa/fixedloadshift.mdwn
@@ -30,12 +30,12 @@
 
 X-Form
 
-* lbzsx RT,RA,RB,sh
+* lbzsx RT,RA,RB,sm
 
 Pseudo-code:
 
     b <- (RA|0)
-    EA <- b + (RB) << (sh+1)
+    EA <- b + (RB) << (sm+1)
     RT <- ([0] * (XLEN-8)) || MEM(EA, 1)
 
 Special Registers Altered:
@@ -46,11 +46,11 @@ Special Registers Altered:
 
 X-Form
 
-* lbzsux RT,RA,RB,sh
+* lbzsux RT,RA,RB,sm
 
 Pseudo-code:
 
-    EA <- (RA) + (RB) << (sh+1)
+    EA <- (RA) + (RB) << (sm+1)
     RT <- ([0] * (XLEN-8)) || MEM(EA, 1)
     RA <- EA
 
@@ -58,16 +58,16 @@ Special Registers Altered:
 
     None
 
-# Load Halfword and Zero Indexed
+# Load Halfword and Zero Shifted Indexed
 
 X-Form
 
-* lhzx RT,RA,RB
+* lhzsx RT,RA,RB,sm
 
 Pseudo-code:
 
     b <- (RA|0)
-    EA <- b + (RB)
+    EA <- b + (RB) (sm+1)
     RT <- ([0] * (XLEN-16)) || MEM(EA, 2)
 
 Special Registers Altered: