From: Zachary Snow <zach@zachjs.com>
Date: Tue, 5 May 2020 00:22:16 +0000 (-0400)
Subject: verilog: allow null gen-if then block
X-Git-Tag: working-ls180~567^2
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=8f9bba1bbfdb56630dadd75a3f92f7bfb26b3df6;p=yosys.git

verilog: allow null gen-if then block
---

diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y
index 4a5aba79e..3738f8f3d 100644
--- a/frontends/verilog/verilog_parser.y
+++ b/frontends/verilog/verilog_parser.y
@@ -2533,7 +2533,12 @@ gen_stmt:
 		ast_stack.back()->children.push_back(node);
 		ast_stack.push_back(node);
 		ast_stack.back()->children.push_back($3);
-	} gen_stmt_block opt_gen_else {
+		AstNode *block = new AstNode(AST_GENBLOCK);
+		ast_stack.back()->children.push_back(block);
+		ast_stack.push_back(block);
+	} gen_stmt_or_null {
+		ast_stack.pop_back();
+	} opt_gen_else {
 		SET_AST_NODE_LOC(ast_stack.back(), @1, @7);
 		ast_stack.pop_back();
 	} |
diff --git a/tests/various/gen_if_null.v b/tests/various/gen_if_null.v
new file mode 100644
index 000000000..a12ac6288
--- /dev/null
+++ b/tests/various/gen_if_null.v
@@ -0,0 +1,13 @@
+module test(x, y, z);
+	localparam OFF = 0;
+	generate
+		if (OFF) ;
+		else input x;
+		if (!OFF) input y;
+		else ;
+		if (OFF) ;
+		else ;
+		if (OFF) ;
+		input z;
+	endgenerate
+endmodule
diff --git a/tests/various/gen_if_null.ys b/tests/various/gen_if_null.ys
new file mode 100644
index 000000000..31dfc444b
--- /dev/null
+++ b/tests/various/gen_if_null.ys
@@ -0,0 +1,4 @@
+read_verilog gen_if_null.v
+select -assert-count 1 test/x
+select -assert-count 1 test/y
+select -assert-count 1 test/z