From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 14 Jun 2019 19:43:20 +0000 (-0700)
Subject: As per @daveshah1 remove async DFF timing from xilinx
X-Git-Tag: working-ls180~1237^2~106
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=8fa74287a71fc3527cf48c7fb2c4a635ee832b72;p=yosys.git

As per @daveshah1 remove async DFF timing from xilinx
---

diff --git a/techlibs/xilinx/abc_xc7.box b/techlibs/xilinx/abc_xc7.box
index a4182ed63..8a48bad4e 100644
--- a/techlibs/xilinx/abc_xc7.box
+++ b/techlibs/xilinx/abc_xc7.box
@@ -54,9 +54,9 @@ FDSE 7 0 4 1
 # Inputs: C CE CLR D
 # Outputs: Q
 FDCE 8 0 4 1
-- - 404 -
+- - - -
 
 # Inputs: C CE D PRE
 # Outputs: Q
 FDPE 9 0 4 1
-- - - 404
+- - - -