From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sun, 14 Apr 2019 14:01:58 +0000 (+0100)
Subject: create flatten and use in eq
X-Git-Tag: div_pipeline~2250
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=8fe3c4a58871f870a9924ea410bc1bfb0ab36dcd;p=soc.git

create flatten and use in eq
---

diff --git a/TLB/src/ariane/ptw.py b/TLB/src/ariane/ptw.py
index 613f07fe..bbaf12d8 100644
--- a/TLB/src/ariane/ptw.py
+++ b/TLB/src/ariane/ptw.py
@@ -18,7 +18,7 @@
 import ariane_pkg::*;
 """
 
-from nmigen import Const, Signal
+from nmigen import Const, Signal, Cat
 from math import log
 
 DCACHE_SET_ASSOC = 8
@@ -45,7 +45,7 @@ class DCacheReqO:
         data_rvalid = Signal()
         data_rdata = Signal(64)
 
-ASID_WIDTH = 1
+ASID_WIDTH = 8
 
 class PTE: #(RecordObject):
     def __init__(self):
@@ -61,12 +61,11 @@ class PTE: #(RecordObject):
         self.r = Signal()
         self.v = Signal()
 
+    def flatten(self):
+        return Cat(*self.ports())
+
     def eq(self, x):
-        return [self.reserved.eq(x.reserved),
-                self.ppn.eq(x.ppn), self.rsw.eq(x.rsw),
-                self.d.eq(x.d), self.a.eq(x.a), self.g.eq(x.g),
-                self.u.eq(x.u), self.x.eq(x.x), self.w.eq(x.w),
-                self.r.eq(x.r), self.v.eq(x.v)]
+        return self.flatten().eq(x.flatten())
 
     def ports(self):
         return [self.reserved, self.ppn, self.rsw, self.d, self.a, self.g,
diff --git a/TLB/src/ariane/tlb.py b/TLB/src/ariane/tlb.py
index ef25510f..bdd0b9aa 100644
--- a/TLB/src/ariane/tlb.py
+++ b/TLB/src/ariane/tlb.py
@@ -19,6 +19,7 @@ from math import log2
 from nmigen import Signal, Module, Cat, Const, Array
 from nmigen.cli import verilog, rtlil
 
+from ptw import TLBUpdate, PTE, ASID_WIDTH
 
 # SV39 defines three levels of page tables
 class TLBEntry:
@@ -32,9 +33,6 @@ class TLBEntry:
         self.valid = Signal()
 
 TLB_ENTRIES = 4
-ASID_WIDTH  = 1
-
-from ptw import TLBUpdate, PTE
 
 
 class TLB:
@@ -182,7 +180,8 @@ class TLB:
                     # lvl0 <=> MSB, lvl1 <=> MSB-1, ...
                     shift = LOG_TLB - lvl;
                     new_idx = Const(~((i >> (shift-1)) & 1), 1)
-                    print ("plru", i, lvl, hex(idx_base), shift, new_idx)
+                    print ("plru", i, lvl, hex(idx_base),
+                                  idx_base + (i >> shift), shift, new_idx)
                     m.d.sync += plru_tree[idx_base + (i >> shift)].eq(new_idx)
 
         # Decode tree to write enable signals
@@ -210,9 +209,9 @@ class TLB:
                 m.d.comb += plru.eq(plru_tree[idx_base + (i>>shift)])
                 # en &= plru_tree_q[idx_base + (i>>shift)] == new_idx;
                 if new_idx:
-                    en[lvl].eq(~plru) # yes inverted (using bool())
+                    m.d.comb += en[lvl].eq(~plru) # yes inverted (using bool())
                 else:
-                    en[lvl].eq(plru)  # yes inverted (using bool())
+                    m.d.comb += en[lvl].eq(plru)  # yes inverted (using bool())
             print ("plru", i, en)
             # boolean logic manipluation:
             # plur0 & plru1 & plur2 == ~(~plru0 | ~plru1 | ~plru2)