From: lkcl <lkcl@web>
Date: Tue, 7 Sep 2021 14:56:37 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: DRAFT_SVP64_0_1~196
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=8fed5cf886a751acafd4044b2a8a62461c8dd603;p=libreriscv.git

---

diff --git a/openpower/sv/cr_ops.mdwn b/openpower/sv/cr_ops.mdwn
index 2e93275b3..43f44f0bb 100644
--- a/openpower/sv/cr_ops.mdwn
+++ b/openpower/sv/cr_ops.mdwn
@@ -15,6 +15,11 @@ be a "co-result". Thus, if the arithmetic result is Vectorised, so
 is the CR Field "co-result", which puts both firmly out of scope for
 this section.
 
+Other modes are still applicable and include:
+
+* Data-dependent fail-first
+* Scalar and parallel reduction
+* Predicate-result
 
 SVP64 RM `MODE` (includes `ELWIDTH` bits) for CR-based operations: