From: Clifford Wolf <clifford@clifford.at>
Date: Tue, 24 Nov 2015 09:51:34 +0000 (+0100)
Subject: Fixed WE/RE usage in iCE40 BRAM mapping
X-Git-Tag: yosys-0.6~62
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=8ff229a3ead38f89b0dddde9d952c8677d89f980;p=yosys.git

Fixed WE/RE usage in iCE40 BRAM mapping
---

diff --git a/techlibs/ice40/brams_map.v b/techlibs/ice40/brams_map.v
index a82161c99..19a61d73b 100644
--- a/techlibs/ice40/brams_map.v
+++ b/techlibs/ice40/brams_map.v
@@ -213,14 +213,14 @@ module \$__ICE40_RAM4K_M0 (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1E
 		.RDATA(A1DATA),
 		.RADDR(A1ADDR_11),
 		.RCLK(CLK2),
-		.RCLKE(1'b1),
-		.RE(A1EN),
+		.RCLKE(A1EN),
+		.RE(1'b1),
 		.WDATA(B1DATA),
 		.WADDR(B1ADDR_11),
 		.MASK(~B1EN),
 		.WCLK(CLK3),
-		.WCLKE(1'b1),
-		.WE(|B1EN)
+		.WCLKE(|B1EN),
+		.WE(1'b1)
 	);
 endmodule
 
@@ -299,13 +299,13 @@ module \$__ICE40_RAM4K_M123 (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B
 		.RDATA(A1DATA_16),
 		.RADDR(A1ADDR_11),
 		.RCLK(CLK2),
-		.RCLKE(1'b1),
-		.RE(A1EN),
+		.RCLKE(A1EN),
+		.RE(1'b1),
 		.WDATA(B1DATA_16),
 		.WADDR(B1ADDR_11),
 		.WCLK(CLK3),
-		.WCLKE(1'b1),
-		.WE(|B1EN)
+		.WCLKE(|B1EN),
+		.WE(1'b1)
 	);
 endmodule