From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Mon, 8 Apr 2019 09:12:19 +0000 (+0100)
Subject: make r_data of ospec type in UnbufferedPipe, and
X-Git-Tag: ls180-24jan2020~1281
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=8ff2a178511e18ea57936c3f14d9d08718593049;p=ieee754fpu.git

make r_data of ospec type in UnbufferedPipe, and
process before putting into r_data
---

diff --git a/src/add/singlepipe.py b/src/add/singlepipe.py
index b3266ddd..d72ac134 100644
--- a/src/add/singlepipe.py
+++ b/src/add/singlepipe.py
@@ -744,9 +744,9 @@ class UnbufferedPipeline(ControlBase):
         self.m = m = ControlBase._elaborate(self, platform)
 
         data_valid = Signal() # is data valid or not
-        r_data = self.stage.ispec() # input type
+        r_data = self.stage.ospec() # output type
         if hasattr(self.stage, "setup"):
-            self.stage.setup(m, r_data)
+            self.stage.setup(m, self.p.i_data)
 
         # some temporaries
         p_i_valid = Signal(reset_less=True)
@@ -759,8 +759,8 @@ class UnbufferedPipeline(ControlBase):
         m.d.sync += data_valid.eq(p_i_valid | \
                                         (~self.n.i_ready_test & data_valid))
         with m.If(pv):
-            m.d.sync += eq(r_data, self.p.i_data)
-        m.d.comb += eq(self.n.o_data, self.stage.process(r_data))
+            m.d.sync += eq(r_data, self.stage.process(self.p.i_data))
+        m.d.comb += eq(self.n.o_data, r_data)
 
         return self.m
 
@@ -837,6 +837,9 @@ class PassThroughHandshake(ControlBase):
     def elaborate(self, platform):
         self.m = m = ControlBase._elaborate(self, platform)
 
+        if hasattr(self.stage, "setup"):
+            self.stage.setup(m, self.p.i_data)
+
         # temporaries
         p_i_valid = Signal(reset_less=True)
         pvr = Signal(reset_less=True)