From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Thu, 3 Jun 2021 15:36:40 +0000 (+0100)
Subject: comment out domains that have already been created
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=900b141682699099ed4a868d7d82899164095758;p=soc.git

comment out domains that have already been created
---

diff --git a/src/soc/simple/issuer.py b/src/soc/simple/issuer.py
index 4f559ce1..1245a6c4 100644
--- a/src/soc/simple/issuer.py
+++ b/src/soc/simple/issuer.py
@@ -1292,6 +1292,11 @@ class TestIssuer(Elaboratable):
         # internal clock is set to selector clock-out.  has the side-effect of
         # running TestIssuer at this speed (see DomainRenamer("intclk") above)
         # debug clock runs at coresync internal clock
+        cd_coresync = ClockDomain("coresync")
+        #m.domains += cd_coresync
+        if self.ti.dbg_domain != 'sync':
+            cd_dbgsync = ClockDomain("dbgsync")
+            #m.domains += cd_dbgsync
         intclk = ClockSignal("coresync")
         dbgclk = ClockSignal(self.ti.dbg_domain)
         # XXX BYPASS PLL XXX