From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sat, 1 Oct 2022 23:35:08 +0000 (+0100)
Subject: skip svstate_pre_inc on svremap
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=9010b20046854994de454b12c94c21f8222ca160;p=openpower-isa.git

skip svstate_pre_inc on svremap
should not be needed
---

diff --git a/src/openpower/decoder/isa/caller.py b/src/openpower/decoder/isa/caller.py
index 3b94fe2c..6919cd74 100644
--- a/src/openpower/decoder/isa/caller.py
+++ b/src/openpower/decoder/isa/caller.py
@@ -1692,7 +1692,7 @@ class ISACaller(ISACallerHelper, ISAFPHelpers, StepLoop):
 
         # see if srcstep/dststep need skipping over masked-out predicate bits
         self.reset_remaps()
-        if (self.is_svp64_mode or ins_name in ['svstep', 'svremap']):
+        if (self.is_svp64_mode or ins_name in ['svstep']):
             yield from self.svstate_pre_inc()
         if self.is_svp64_mode:
             pre = yield from self.update_new_svstate_steps()